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Message-ID: <9a7f9aa0-ff88-44d0-a3de-4f38835a5cd2@intel.com>
Date: Fri, 28 Mar 2025 07:12:37 -0700
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: Chao Gao <chao.gao@...el.com>
CC: <linux-kernel@...r.kernel.org>, <x86@...nel.org>, <tglx@...utronix.de>,
<mingo@...hat.com>, <bp@...en8.de>, <dave.hansen@...ux.intel.com>,
<colinmitchell@...gle.com>
Subject: Re: [PATCH v2a 3/6] x86/microcode/intel: Establish staging control
logic
On 3/26/2025 6:44 PM, Chao Gao wrote:
>
> The check I suggested can also achieve the goal and is simpler, right?
Okay, I’d (finally) define this mask compilable for CONFIG_SMP=n, in
topology.h:
#define cpu_primary_thread_mask cpu_none_mask
Then,
for_each_cpu(cpu, cpu_primary_thread_mask) {
if (topology_logical_package_id(cpu) == pkg_id)
continue;
...
}
This still looks simpler. Plus, while timing isn’t a major concern on
this staging path, cpumask_first() on every CPU appears costly. On my
measurements, this takes about a third of the time compared to yours.
Thanks,
Chang
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