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Message-ID: <20250330210717.46080-16-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 30 Mar 2025 22:07:11 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Biju Das <biju.das.jz@...renesas.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Kieran Bingham <kieran.bingham+renesas@...asonboard.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>
Cc: devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
linux-media@...r.kernel.org,
linux-clk@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 15/17] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs,
function pointers are introduced.
Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock
configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke
`dphy_mode_clk_check` for mode validation.
This change ensures proper operation across different SoC variants
by allowing fine-grained control over clock configuration and mode
validation.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 59 +++++++++++++------
1 file changed, 42 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index 143bb01e6f50..2ca725a2ccaf 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -36,6 +36,10 @@ struct rzg2l_mipi_dsi_hw_info {
int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz);
void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi);
void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
+ int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
+ unsigned long long *hsfreq_mhz);
+ unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,
+ unsigned long mode_freq);
u32 phy_reg_offset;
u32 link_reg_offset;
unsigned long max_dclk;
@@ -276,12 +280,36 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
reset_control_assert(dsi->rstc);
}
+static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
+ unsigned long long *hsfreq_mhz)
+{
+ unsigned long vclk_rate;
+ unsigned int bpp;
+
+ clk_set_rate(dsi->vclk, mode_freq * KILO);
+ /*
+ * Relationship between hsclk and vclk must follow
+ * vclk * bpp = hsclk * 8 * lanes
+ * where vclk: video clock (Hz)
+ * bpp: video pixel bit depth
+ * hsclk: DSI HS Byte clock frequency (Hz)
+ * lanes: number of data lanes
+ *
+ * hsclk(bit) = hsclk(byte) * 8 = hsfreq
+ */
+ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ vclk_rate = clk_get_rate(dsi->vclk);
+ *hsfreq_mhz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL,
+ dsi->lanes);
+
+ return 0;
+}
+
static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
const struct drm_display_mode *mode)
{
- unsigned long hsfreq, vclk_rate;
unsigned long long hsfreq_mhz;
- unsigned int bpp;
+ unsigned long hsfreq;
u32 txsetr;
u32 clstptsetr;
u32 lptrnstsetr;
@@ -295,21 +323,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
if (ret < 0)
return ret;
- clk_set_rate(dsi->vclk, mode->clock * KILO);
-
- /*
- * Relationship between hsclk and vclk must follow
- * vclk * bpp = hsclk * 8 * lanes
- * where vclk: video clock (Hz)
- * bpp: video pixel bit depth
- * hsclk: DSI HS Byte clock frequency (Hz)
- * lanes: number of data lanes
- *
- * hsclk(bit) = hsclk(byte) * 8 = hsfreq
- */
- bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
- vclk_rate = clk_get_rate(dsi->vclk);
- hsfreq_mhz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes);
+ ret = dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_mhz);
+ if (ret < 0)
+ goto err_phy;
ret = dsi->info->dphy_init(dsi, hsfreq_mhz);
if (ret < 0)
@@ -617,6 +633,14 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
if (mode->clock < dsi->info->min_dclk)
return MODE_CLOCK_LOW;
+ if (dsi->info->dphy_mode_clk_check) {
+ enum drm_mode_status status;
+
+ status = dsi->info->dphy_mode_clk_check(dsi, mode->clock);
+ if (status != MODE_OK)
+ return status;
+ }
+
return MODE_OK;
}
@@ -839,6 +863,7 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {
.dphy_init = rzg2l_mipi_dsi_dphy_init,
.dphy_exit = rzg2l_mipi_dsi_dphy_exit,
+ .dphy_conf_clks = rzg2l_dphy_conf_clks,
.has_dphy_rstc = true,
.link_reg_offset = 0x10000,
.max_dclk = 148500,
--
2.49.0
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