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Message-ID: <20250330083659.61c52d2b@wsk>
Date: Sun, 30 Mar 2025 08:36:59 +0200
From: Lukasz Majewski <lukma@...x.de>
To: Andrew Lunn <andrew@...n.ch>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, davem@...emloft.net, Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
<pabeni@...hat.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Shawn Guo
<shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, Pengutronix
Kernel Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>,
Richard Cochran <richardcochran@...il.com>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/4] dt-bindings: net: Add MTIP L2 switch description
Hi Andrew,
> > + ethphy0: ethernet-phy@0 {
> > + reg = <0>;
> > + smsc,disable-energy-detect;
> > + /* Both PHYs (i.e. 0,1) have the same,
> > single GPIO, */
> > + /* line to handle both, their interrupts
> > (AND'ed) */
> > + interrupt-parent = <&gpio4>;
> > + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
>
> Shared interrupts cannot be edge. They are level, so that either can
> hold the interrupt active until it is cleared.
>
> Also, PHY interrupts in general are level, because there are multiple
> interrupt sources within the PHY, and you need to clear them all
> before the interrupt is released.
Good point, I will update it accordingly. Thanks.
>
> Andrew
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
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Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@...x.de
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