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Message-Id: <20250331-imx8_pcie_ep_dts-v1-1-270ef0868ac9@nxp.com>
Date: Mon, 31 Mar 2025 15:02:39 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>
Cc: devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
hongxing.zhu@....com, Frank Li <Frank.Li@....com>
Subject: [PATCH 1/8] arm64: dts: imx8: create unified pcie0 and pcie0_ep
label for all chips
Add unified pcie<n> and pcie<n>_ep label for existed chipes to prepare
applied one overay file to enable EP function.
Signed-off-by: Frank Li <Frank.Li@....com>
---
arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 23 ++++++++++++----------
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++--
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 6 +++---
arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi | 6 ++++++
4 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
index afbe962d78ce1..67c5c6029cd9b 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
@@ -37,15 +37,18 @@ hsio_phy: phy@...a0000 {
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
-};
-&pcieb {
- #interrupt-cells = <1>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- interrupt-map = <0 0 0 1 &gic 0 47 4>,
- <0 0 0 2 &gic 0 48 4>,
- <0 0 0 3 &gic 0 49 4>,
- <0 0 0 4 &gic 0 50 4>;
- interrupt-map-mask = <0 0 0 0x7>;
+ pcie0: pcie@...10000 {
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map = <0 0 0 1 &gic 0 47 4>,
+ <0 0 0 2 &gic 0 48 4>,
+ <0 0 0 3 &gic 0 49 4>,
+ <0 0 0 4 &gic 0 50 4>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ };
+
+ pcie0_ep: pcie-ep@...10000 {
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ce6793b2d57ee..b955db19f3bd5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2155,7 +2155,7 @@ hdmi_tx_phy: phy@...dff00 {
};
};
- pcie: pcie@...00000 {
+ pcie0: pcie: pcie@...00000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
@@ -2193,7 +2193,7 @@ pcie: pcie@...00000 {
status = "disabled";
};
- pcie_ep: pcie-ep@...00000 {
+ pcie0_ep: pcie_ep: pcie-ep@...00000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x33800000 0x100000>,
<0x18000000 0x8000000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index e80f722dbe65f..50c0f6b0f0bdc 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -12,7 +12,7 @@ &hsio_subsys {
#address-cells = <1>;
#size-cells = <1>;
- pciea: pcie@...00000 {
+ pcie0: pciea: pcie@...00000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f000000 0x10000>,
<0x4ff00000 0x80000>;
@@ -42,7 +42,7 @@ pciea: pcie@...00000 {
status = "disabled";
};
- pciea_ep: pcie-ep@...00000 {
+ pcie0_ep: pciea_ep: pcie-ep@...00000 {
compatible = "fsl,imx8q-pcie-ep";
reg = <0x5f000000 0x00010000>,
<0x40000000 0x10000000>;
@@ -61,7 +61,7 @@ pciea_ep: pcie-ep@...00000 {
status = "disabled";
};
- pcieb: pcie@...10000 {
+ pcie1: pcieb: pcie@...10000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>,
<0x8ff00000 0x80000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
index 47fc6e0cff4a1..255b8c91c88cc 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
@@ -38,4 +38,10 @@ hsio_phy: phy@...a0000 {
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
+
+ pcie0: pcie@...10000 {
+ };
+
+ pcie0_ep: pcie-ep@...10000 {
+ };
};
--
2.34.1
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