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Message-ID:
<TYCPR01MB11332E15E9A94C41A6D46F3FF86AD2@TYCPR01MB11332.jpnprd01.prod.outlook.com>
Date: Mon, 31 Mar 2025 10:13:09 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>, Prabhakar
<prabhakar.csengg@...il.com>
CC: Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Magnus Damm
<magnus.damm@...il.com>, "linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>, "linux-clk@...r.kernel.org"
<linux-clk@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, Fabrizio Castro
<fabrizio.castro.jz@...esas.com>, Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH 0/6] clk: renesas: rzv2h: Add clock and reset entries for
USB2 and GBETH
Hi Geert,
> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 31 March 2025 10:57
> Subject: Re: [PATCH 0/6] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH
>
> Hi Prabhakar (and Biju),
>
> On Fri, 28 Mar 2025 at 21:01, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > Note, these patch apply on top of the following patch series:
> > https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-
> > lad.rj@...renesas.com/
>
> That patch series was ultimately ignored because it was not clear how it related to other similar
> patches for the same driver. So please coordinate and resend, based on renesas-clk-for-v6.16, or even
> better,
> v6.15-rc1 next week.
DEF_CSDIV macro for clk divider with custom code as it requires RMW operation.
and
DEF_SDIV macro for clk divider with generic API.
So, you mean use DEF_CSDIV macro for clk divider with generic API ??
Cheers,
Biju
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