linux-kernel - Re: [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer

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Message-ID: <4267a636-d858-55f0-01fe-c5d7265ed3c6@oss.nxp.com>
Date: Mon, 31 Mar 2025 13:55:45 +0300
From: Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>, wim@...ux-watchdog.org
Cc: linux@...ck-us.net, linux-watchdog@...r.kernel.org,
 linux-kernel@...r.kernel.org, S32@....com,
 Ghennadi Procopciuc <ghennadi.procopciuc@....com>,
 Thomas Fossati <thomas.fossati@...aro.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>,
 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
 <devicetree@...r.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog
 Timer

On 3/28/2025 5:15 PM, Daniel Lezcano wrote:
> Describe the Software Watchdog Timer available on the S32G platforms.
> 
> Cc: Ghennadi Procopciuc <ghennadi.procopciuc@....com>
> Cc: Thomas Fossati <thomas.fossati@...aro.org>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
> ---
>  .../bindings/watchdog/nxp,s32g-wdt.yaml       | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
> new file mode 100644
> index 000000000000..06ead743d5c1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/watchdog/nxp,s32g-wdt.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP Software Watchdog Timer
> +
> +maintainers:
> +  - Daniel Lezcano <daniel.lezcano@...nel.org>
> +
> +description:
> +  The System Timer Module supports commonly required system and
> +  application software timing functions. STM includes a 32-bit
> +  count-up timer and four 32-bit compare channels with a separate
> +  interrupt source for each channel. The timer is driven by the STM
> +

Please update the description, as this one refers to STM instead of SWT.

-- 
Regards,
Ghennadi