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Message-ID: <Z-xP3M7-GSUCHQkb@ghost>
Date: Tue, 1 Apr 2025 13:43:08 -0700
From: Charlie Jenkins <charlie@...osinc.com>
To: Nathan Chancellor <nathan@...nel.org>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Ard Biesheuvel <ardb@...nel.org>,
Ben Dooks <ben.dooks@...ethink.co.uk>,
Pasha Bouzarjomehri <pasha@...osinc.com>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Alexandre Ghiti <alexghiti@...osinc.com>,
Steven Rostedt <rostedt@...dmis.org>,
Masami Hiramatsu <mhiramat@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Albert Ou <aou@...s.berkeley.edu>,
Peter Zijlstra <peterz@...radead.org>,
Josh Poimboeuf <jpoimboe@...nel.org>,
Jason Baron <jbaron@...mai.com>,
Andrew Jones <ajones@...tanamicro.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-trace-kernel@...r.kernel.org, llvm@...ts.linux.dev
Subject: Re: [PATCH v10 2/2] riscv: Add runtime constant support
On Tue, Apr 01, 2025 at 12:28:33PM -0700, Nathan Chancellor wrote:
> Hi Charlie,
>
> On Wed, Mar 19, 2025 at 11:35:20AM -0700, Charlie Jenkins wrote:
> > Implement the runtime constant infrastructure for riscv. Use this
> > infrastructure to generate constants to be used by the d_hash()
> > function.
> >
> > This is the riscv variant of commit 94a2bc0f611c ("arm64: add 'runtime
> > constant' support") and commit e3c92e81711d ("runtime constants: add
> > x86 architecture support").
> >
> > Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> > Reviewed-by: Alexandre Ghiti <alexghiti@...osinc.com>
> ...
> > diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/asm/runtime-const.h
> ...
> > +#define RISCV_RUNTIME_CONST_64_ZBA \
> > + ".option push\n\t" \
> > + ".option arch,+zba\n\t" \
> > + "slli %[__tmp],%[__tmp],32\n\t" \
> > + "add.uw %[__ret],%[__ret],%[__tmp]\n\t" \
> > + "nop\n\t" \
> > + "nop\n\t" \
> > + ".option pop\n\t" \
> ...
> > +#if defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_RISCV_ISA_ZBKB)
> ...
> > +#elif defined(CONFIG_RISCV_ISA_ZBA)
> > +#define runtime_const_ptr(sym) \
> > +({ \
> > + typeof(sym) __ret, __tmp; \
> > + asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \
> > + ALTERNATIVE( \
> > + RISCV_RUNTIME_CONST_64_BASE, \
> > + RISCV_RUNTIME_CONST_64_ZBA, \
> > + 0, RISCV_ISA_EXT_ZBA, 1 \
> > + ) \
> > + RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \
> > + : [__ret] "=r" (__ret), [__tmp] "=r" (__tmp)); \
> > + __ret; \
> > +})
>
> This breaks the build for clang versions 16 and earlier because they do
> not support '.option arch' and it is used in CONFIG_RISCV_ISA_ZBA, which
> has no dependencies and it is default on.
>
> $ make -skj"$(nproc)" ARCH=riscv LLVM=1 mrproper defconfig fs/dcache.o
> fs/dcache.c:117:9: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax' [-Winline-asm]
> return runtime_const_ptr(dentry_hashtable) +
> ^
> arch/riscv/include/asm/runtime-const.h:103:4: note: expanded from macro 'runtime_const_ptr'
> RISCV_RUNTIME_CONST_64_ZBA, \
> ^
> arch/riscv/include/asm/runtime-const.h:57:17: note: expanded from macro 'RISCV_RUNTIME_CONST_64_ZBA'
> ".option push\n\t" \
> ^
> <inline asm>:32:10: note: instantiated into assembly here
> .option arch,+zba
> ^
> fs/dcache.c:117:9: error: instruction requires the following: 'Zba' (Address Generation Instructions)
> return runtime_const_ptr(dentry_hashtable) +
> ^
> arch/riscv/include/asm/runtime-const.h:103:4: note: expanded from macro 'runtime_const_ptr'
> RISCV_RUNTIME_CONST_64_ZBA, \
> ^
> arch/riscv/include/asm/runtime-const.h:59:30: note: expanded from macro 'RISCV_RUNTIME_CONST_64_ZBA'
> "slli %[__tmp],%[__tmp],32\n\t" \
> ^
> <inline asm>:34:2: note: instantiated into assembly here
> add.uw a2,a2,a3
> ^
> ...
>
> $ rg 'OPTION_ARCH|ZBA' .config
> 364:CONFIG_RISCV_ISA_ZBA=y
>
> Should it grow a dependency on AS_HAS_OPTION_ARCH or should there be a
> different fix?
This should have been fixed by Alex's patch [1]. Zba is in an awkward
state because BPF generates Zba code without the need for toolchain
support.
[1] https://lore.kernel.org/all/20250328115422.253670-1-alexghiti@rivosinc.com/
>
> Cheers,
> Nathan
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