linux-kernel - RE: [PATCH v6 02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID:
 <TYCPR01MB11492A8B94D939907DC79F1BD8AAC2@TYCPR01MB11492.jpnprd01.prod.outlook.com>
Date: Tue, 1 Apr 2025 12:20:38 +0000
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: Rob Herring <robh@...nel.org>
CC: "thierry.bultel@...atsea.fr" <thierry.bultel@...atsea.fr>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"geert@...ux-m68k.org" <geert@...ux-m68k.org>, Paul Barker
	<paul.barker.ct@...renesas.com>, Geert Uytterhoeven
	<geert+renesas@...der.be>, "linux-clk@...r.kernel.org"
	<linux-clk@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v6 02/13] dt-bindings: clock: Add cpg for the Renesas
 RZ/T2H SoC

Hi Rob, 
thanks for your review,

> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > index 77ce3615c65a..dee4c44ef025 100644
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > @@ -52,9 +52,11 @@ properties:
> >        - renesas,r8a779f0-cpg-mssr # R-Car S4-8
> >        - renesas,r8a779g0-cpg-mssr # R-Car V4H
> >        - renesas,r8a779h0-cpg-mssr # R-Car V4M
> > +      - renesas,r9a09g077-cpg-mssr # RZ/T2H
> >
> >    reg:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> 
> You need to define what each entry is. And do that here assuming the first
> entry is the same in either case.

Would this be the right way ? (maxItems become implicit)


  reg:
    minItems: 1
    items:
      - description: base address of register block 0
      - description: base address of register block 1
    description: base addresses of clock controller. Some controllers
      (like r9a09g077) use two blocks instead of a single one).


Thanks !
Thierry