linux-kernel - Re: [PATCH v5 03/18] drm/imagination: Update register defs for newer GPUs

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Message-ID: <f8a0769425365e6e0e0e7bb547cc1347ebbf872d.camel@imgtec.com>
Date: Tue, 1 Apr 2025 13:40:43 +0000
From: Frank Binns <Frank.Binns@...tec.com>
To: "tzimmermann@...e.de" <tzimmermann@...e.de>,
        "simona@...ll.ch"
	<simona@...ll.ch>,
        Matt Coster <Matt.Coster@...tec.com>,
        "kristo@...nel.org"
	<kristo@...nel.org>,
        "robh@...nel.org" <robh@...nel.org>,
        "airlied@...il.com"
	<airlied@...il.com>,
        "krzk+dt@...nel.org" <krzk+dt@...nel.org>, "nm@...com"
	<nm@...com>,
        "maarten.lankhorst@...ux.intel.com"
	<maarten.lankhorst@...ux.intel.com>,
        "conor+dt@...nel.org"
	<conor+dt@...nel.org>,
        "mripard@...nel.org" <mripard@...nel.org>,
        "vigneshr@...com" <vigneshr@...com>
CC: "detheridge@...com" <detheridge@...com>, "rs@...com" <rs@...com>,
        "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Alessio Belle
	<Alessio.Belle@...tec.com>,
        "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>,
        "m.wilczynski@...sung.com"
	<m.wilczynski@...sung.com>,
        Alexandru Dadu <Alexandru.Dadu@...tec.com>
Subject: Re: [PATCH v5 03/18] drm/imagination: Update register defs for newer
 GPUs

On Wed, 2025-03-26 at 16:48 +0000, Matt Coster wrote:
> From: Alessio Belle <alessio.belle@...tec.com>
> 
> Update the register define header to a newer version that covers more
> recent GPUs, including BXS-4-64.
> 
> Signed-off-by: Alessio Belle <alessio.belle@...tec.com>
> Signed-off-by: Matt Coster <matt.coster@...tec.com>

Patches 3-16 are:

Reviewed-by: Frank Binns <frank.binns@...tec.com>

Thanks
Frank

> ---
> Changes in v5:
> - None
> - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-3-d987cf4ca439@imgtec.com
> Changes in v4:
> - None
> - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-3-143b3dbef02f@imgtec.com
> Changes in v3:
> - Added
> ---
>  drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 153 +++++++++++++++++++++---
>  1 file changed, 134 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> index 2a90d02796d3e071b18e18dead105e29798bcddc..790c97f80a2ac03ac76b933d009a2f9cfc6003f7 100644
> --- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> +++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> @@ -827,6 +827,120 @@
>  #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
>  #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U
>  
> +/* Register ROGUE_CR_EVENT_CLEAR */
> +#define ROGUE_CR_EVENT_CLEAR 0x0138U
> +#define ROGUE_CR_EVENT_CLEAR__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL
> +#define ROGUE_CR_EVENT_CLEAR__SIGNALS__MASKFULL 0x00000000E007FFFFULL
> +#define ROGUE_CR_EVENT_CLEAR_MASKFULL 0x00000000FFFFFFFFULL
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT 31U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN 0x80000000U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT 30U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN 0x40000000U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT 29U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_SHIFT 28U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_EN 0x10000000U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_SHIFT 27U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_EN 0x08000000U
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_SHIFT 26U
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_EN 0x04000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_SHIFT 25U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_EN 0x02000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_SHIFT 24U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_EN 0x01000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_SHIFT 23U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_EN 0x00800000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_SHIFT 22U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_EN 0x00400000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_SHIFT 21U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_EN 0x00200000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_SHIFT 20U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_EN 0x00100000U
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_SHIFT 20U
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_CLRMSK 0xFFEFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_EN 0x00100000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_SHIFT 19U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_EN 0x00080000U
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_SHIFT 19U
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_CLRMSK 0xFFF7FFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_EN 0x00080000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_SHIFT 18U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_EN 0x00040000U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_SHIFT 17U
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_CLRMSK 0xFFFDFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_EN 0x00020000U
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT 17U
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT 16U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN 0x00010000U
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT 15U
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK 0xFFFF7FFFU
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_EN 0x00008000U
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_SHIFT 14U
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_EN 0x00004000U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_SHIFT 13U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK 0xFFFFDFFFU
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_EN 0x00002000U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_SHIFT 12U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK 0xFFFFEFFFU
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_EN 0x00001000U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_SHIFT 11U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK 0xFFFFF7FFU
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_EN 0x00000800U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT 10U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_EN 0x00000400U
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT 9U
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN 0x00000200U
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_SHIFT 8U
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_EN 0x00000100U
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT 7U
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN 0x00000080U
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT 6U
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK 0xFFFFFFBFU
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_EN 0x00000040U
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_SHIFT 5U
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK 0xFFFFFFDFU
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_EN 0x00000020U
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT 4U
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN 0x00000010U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_SHIFT 3U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_EN 0x00000008U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT 2U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN 0x00000004U
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT 1U
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_EN 0x00000002U
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_SHIFT 0U
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_EN 0x00000001U
> +
>  /* Register ROGUE_CR_TIMER */
>  #define ROGUE_CR_TIMER 0x0160U
>  #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL
> @@ -6031,25 +6145,6 @@
>  #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
>  #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
>  
> -/* Register ROGUE_CR_ECC_RAM_ERR_INJ */
> -#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U
> -
>  /* Register ROGUE_CR_ECC_RAM_INIT_KICK */
>  #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U
>  #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL
> @@ -6163,6 +6258,26 @@
>  #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
>  #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
>  
> +/* Register ROGUE_CR_FAULT_FW_STATUS */
> +#define ROGUE_CR_FAULT_FW_STATUS 0xF3B0U
> +#define ROGUE_CR_FAULT_FW_STATUS_MASKFULL 0x0000000000010001ULL
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_SHIFT 16U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_EN 0x00010000U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_SHIFT 0U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_EN 0x00000001U
> +
> +/* Register ROGUE_CR_FAULT_FW_CLEAR */
> +#define ROGUE_CR_FAULT_FW_CLEAR 0xF3B8U
> +#define ROGUE_CR_FAULT_FW_CLEAR_MASKFULL 0x0000000000010001ULL
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_SHIFT 16U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_EN 0x00010000U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_SHIFT 0U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_EN 0x00000001U
> +
>  /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */
>  #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U
>  #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
>