linux-kernel - RE: [PATCH v3 5/6] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

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Message-ID:
 <AS8PR04MB8676079CE89A325C2B98A8E98CAF2@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Wed, 2 Apr 2025 07:40:30 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
CC: Frank Li <frank.li@....com>, "l.stach@...gutronix.de"
	<l.stach@...gutronix.de>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kw@...ux.com" <kw@...ux.com>, "robh@...nel.org" <robh@...nel.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "shawnguo@...nel.org"
	<shawnguo@...nel.org>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
	"kernel@...gutronix.de" <kernel@...gutronix.de>, "festevam@...il.com"
	<festevam@...il.com>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 5/6] PCI: imx6: Add PLL clock lock check for i.MX95
 PCIe


> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Sent: 2025年4月2日 15:10
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de; lpieralisi@...nel.org;
> kw@...ux.com; robh@...nel.org; bhelgaas@...gle.com;
> shawnguo@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> festevam@...il.com; linux-pci@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; imx@...ts.linux.dev;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v3 5/6] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe
> 
> On Fri, Mar 28, 2025 at 11:02:12AM +0800, Richard Zhu wrote:
> > Add PLL clock lock check for i.MX95 PCIe.
> >
> 
> What are the implications of not waiting for PLL lock? I guess clock instability.
>
Yes, it is. 
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > Reviewed-by: Frank Li <Frank.Li@....com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 28
> > +++++++++++++++++++++++++--
> >  1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 35194b543551..40eeb02ffb5d 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -45,6 +45,9 @@
> >  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
> >  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
> >
> > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> > +
> >  #define IMX95_PCIE_SS_RW_REG_0			0xf0
> >  #define IMX95_PCIE_REF_CLKEN			BIT(23)
> >  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > @@ -479,6 +482,23 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct
> imx_pcie *imx_pcie)
> >  		dev_err(dev, "PCIe PLL lock timeout\n");  }
> >
> > +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie
> > +*imx_pcie) {
> > +	u32 val;
> > +	struct device *dev = imx_pcie->pci->dev;
> > +
> > +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> > +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> > +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> > +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> > +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> > +		dev_err(dev, "PCIe PLL lock timeout\n");
> > +		return -ENODEV;
> 
> -ETIMEDOUT
Okay

Best Regards
Richard Zhu
> 
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்