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Message-ID: <20250402092134.12293-2-xiangzhi.tang@mediatek.com>
Date: Wed, 2 Apr 2025 17:19:24 +0800
From: Xiangzhi Tang <xiangzhi.tang@...iatek.com>
To: Bjorn Andersson <andersson@...nel.org>, Mathieu Poirier
<mathieu.poirier@...aro.org>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Matthias
Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Xiangzhi Tang
<Xiangzhi.Tang@...iatek.com>
CC: <linux-remoteproc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
<jjian.zhou@...iatek.com>, <hailong.fan@...iatek.com>, Xiangzhi Tang
<xiangzhi.tang@...iatek.com>
Subject: [PATCH 1/2] dt-bindings: remoteproc: Add VCP support for mt8196
Add the new binding document for MediaTek Video Companion
Processor(VCP) on MediaTek mt8196.
Signed-off-by: Xiangzhi Tang <xiangzhi.tang@...iatek.com>
---
.../remoteproc/mediatek,mt8196-vcp.yaml | 174 ++++++++++++++++++
1 file changed, 174 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml b/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml
new file mode 100644
index 000000000000..0c2926e29c02
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/mediatek,mt8196-vcp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Video Companion Processor (VCP)
+
+maintainers:
+ - Xiangzhi Tang <Xiangzhi.Tang@...iatek.com>
+
+description:
+ The MediaTek VCP enables the SoC control the MediaTek Video Companion Risc-V coprocessor.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-vcp
+
+ reg:
+ items:
+ - description: sram base
+ - description: cfg group IO
+ - description: cfg core group IO
+ - description: cfg sec group IO
+ - description: vcp rdy group IO
+
+ reg-names:
+ items:
+ - const: sram
+ - const: cfg
+ - const: cfg_core
+ - const: cfg_sec
+ - const: vcp_vlp_ao_rsvd7
+
+ interrupts:
+ maxItems: 1
+
+ mboxes:
+ description:
+ Using mailbox to communicate with VCP, it should have this
+ property and list of phandle, mailbox specifiers. See
+ Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
+ for details.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mbox-names:
+ maxItems: 5
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ maxItems: 1
+
+ iommus:
+ description:
+ Using MediaTek iommu to apply larb ports for Multimedia Memory
+ Management Unit and address translation
+ Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+
+ memory-region:
+ maxItems: 1
+
+ vcp-mem-tbl:
+ description:
+ Manage reserved memory for VCP RTOS FW and various features.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 12
+
+patternProperties:
+ "^vcp_[a-f0-9]+$":
+ type: object
+ description:
+ The MediaTek VCP integrated to SoC might be a multi-core version.
+ The other cores are represented as child nodes of the boot core.
+ There are some integration differences for the IP like the usage of
+ address translator for translating SoC bus addresses into address
+ space for the processor.
+
+ The SRAM are shared by all cores, each VCP core only using a piece
+ SRAM memory. The power of SRAM should be enabled before booting VCP cores.
+ The size of SRAM are varied on differnt SoCs.
+
+ The VCP cores has differences on different SoCs to support for
+ Hart.
+
+ properties:
+ compatible:
+ enum:
+ - mediatek,vcp-core
+ - mediatek,mmup-core
+
+ twohart:
+ enum: [0, 1]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ sram-offset:
+ description:
+ Allocated SRAM memory for each VCP core used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - compatible
+ - twohart
+ - sram-offset
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - mboxes
+ - mbox-names
+ - power-domains
+ - iommus
+ - memory-region
+ - vcp-mem-tbl
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8196-power.h>
+
+ vcp: vcp@...00000 {
+ compatible = "mediatek,mt8196-vcp";
+ reg = <0x31800000 0x60000>,
+ <0x31a04000 0xa000>,
+ <0x31bd0000 0x1000>,
+ <0x31a70020 0x100>,
+ <0x1c00091c 0x4>;
+ reg-names = "sram",
+ "cfg",
+ "cfg_core",
+ "cfg_sec",
+ "vcp_vlp_ao_rsvd7";
+
+ interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ mboxes = <&vcp_mailbox0>,
+ <&vcp_mailbox1>,
+ <&vcp_mailbox2>,
+ <&vcp_mailbox3>,
+ <&vcp_mailbox4>;
+ mbox-names = "mbox0", "mbox1", "mbox2", "mbox3", "mbox4";
+
+ power-domains = <&scpsys MT8196_POWER_DOMAIN_MM_PROC_DORMANT>;
+ iommus = <&mm_smmu 160>;
+ memory-region = <&vcp_resv_mem>;
+ vcp-mem-tbl = <0 0x1a00000>,
+ <1 0x30000>,
+ <2 0x12000>,
+ <3 0x1000>,
+ <4 0x1000>,
+ <5 0x1000>;
+ vcp_0 {
+ compatible = "mediatek,vcp-core";
+ twohart = <1>;
+ sram-offset = <0x0>;
+ };
+
+ vcp_1 {
+ compatible = "mediatek,mmup-core";
+ twohart = <0>;
+ sram-offset = <0x31000>;
+ };
+ };
--
2.45.2
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