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Message-ID: <CAGXv+5GuUm0LMphTMvV-A9zebOfyb1sAG+QyQ0jhrF7TV5M48w@mail.gmail.com>
Date: Wed, 2 Apr 2025 17:24:05 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-mediatek@...ts.infradead.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, matthias.bgg@...il.com, weiyi.lu@...iatek.com,
tinghan.shen@...iatek.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kernel@...labora.com
Subject: Re: [PATCH v1 2/2] arm64: dts: mediatek: mt8195: Reparent vdec1/2 and
venc1 power domains
On Wed, Apr 2, 2025 at 5:11 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> By hardware, the first and second core of the video decoder IP
> need the VDEC_SOC to be powered up in order to be able to be
> accessed (both internally, by firmware, and externally, by the
> kernel).
> Similarly, for the video encoder IP, the second core needs the
> first core to be powered up in order to be accessible.
>
> Fix that by reparenting the VDEC1/2 power domains to be children
> of VDEC0 (VDEC_SOC), and the VENC1 to be a child of VENC0.
>
> Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Changes look correct. Would need MediaTek to confirm whether the power
domain hierarchy matches what is claimed here.
Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
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