[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <67ed4792b475_7190f294ce@iweiny-mobl.notmuch>
Date: Wed, 2 Apr 2025 09:20:02 -0500
From: Ira Weiny <ira.weiny@...el.com>
To: Gregory Price <gourry@...rry.net>, Dan Williams <dan.j.williams@...el.com>
CC: "Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>, "Davidlohr
Bueso" <dave@...olabs.net>, Jonathan Cameron <jonathan.cameron@...wei.com>,
Dave Jiang <dave.jiang@...el.com>, Alison Schofield
<alison.schofield@...el.com>, Vishal Verma <vishal.l.verma@...el.com>, "Ira
Weiny" <ira.weiny@...el.com>, Robert Richter <rrichter@....com>,
<ming.li@...omail.com>, <linux-kernel@...r.kernel.org>,
<linux-cxl@...r.kernel.org>
Subject: Re: [PATCH 2/4 v2] cxl/core: Add helpers to detect Low memory Holes
on x86
Gregory Price wrote:
> On Tue, Apr 01, 2025 at 04:34:44PM -0700, Dan Williams wrote:
> > The platforms with this condition want to support CXL mapped starting at
> > zero *and* the typical/historical PCI MMIO space in low memory (for
> > those PCI devices that do not support 64-bit addressing). If the CFMWS
> > blindly followed the 256MB*NIW constraint the CXL window would overlap
> > the MMIO space. So the choices are:
> >
>
> If I'm understanding everything correctly, then I think this is intended
> to work only when EFI_MEMORY_SP is *not* set for these particular CXL
> devices - so it comes up as memory in early boot and we're just trying
> to wire up all the bits to let the driver manage it accordingly?
That is how I understand things. But I'm just jumping in just to review
the patches so I could be wrong...
Ira
>
> If that's the case, then ignore me, i'm just bikeshedding at this point.
>
> I can't imagine a system where the memory at 0x0-4GB is intended to come
> up as EFI_MEMORY_SP, so I hope no one ever tries this :D
>
> > > (Also, I still don't understand the oracle value of <4GB address range.
> > > It seems like if this is some quirk of SPA vs HPA alignment, then it
> > > can hold for *all* ocurrances, not just stuff below 4GB)
> >
> > The goal is to get platform vendors to define the rules so that an OS
> > has a reasonable expectation to know what is a valid vs invalid
> > configuration. A hole above 4GB has no reason to exist, there is no
> > resource conflict like PCI MMIO that explains why typical spec
> > expectation can not be met.
> >
> > So I want the subsystem to have an explicit set of platform quirks
> > ideally backed up by updated spec language. That allows us to validate
> > that the Linux implementation is correct by some objective source of
> > truth, encourage platform vendors to update that source of truth when
> > they create new corner cases, or even better, be more mindful to not
> > create new corner cases.
>
> I follow, seems reasonable.
>
> ~Gregory
Powered by blists - more mailing lists