lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <8734epyw17.wl-maz@kernel.org>
Date: Thu, 03 Apr 2025 18:50:12 +0100
From: Marc Zyngier <maz@...nel.org>
To: Christian Bruel <christian.bruel@...s.st.com>
Cc: <tglx@...utronix.de>,
	<robh@...nel.org>,
	<krzk+dt@...nel.org>,
	<conor+dt@...nel.org>,
	<mcoquelin.stm32@...il.com>,
	<alexandre.torgue@...s.st.com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>,
	<linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [PATCH 2/3] irqchip/gic: Use 0x10000 offset to access GICC_DIR on STM32MP2

On Thu, 03 Apr 2025 13:28:04 +0100,
Christian Bruel <christian.bruel@...s.st.com> wrote:
> 
> When GIC_4KNOT64K bit in the GIC configuration register is
> 0 (64KB), address block is modified in such a way than only the
> first 4KB of the GIC cpu interface are accessible with default
> offsets.
> With this bit mapping GICC_DIR register is accessible at
> offset 0x10000 instead of 0x1000, thus remap accordingly

And I'm pretty sure the whole of the GICC range is correctly
accessible at offset 0xF000, giving you the full 8kB you need. That's
because each page of the GIC is aliased over two 64kB blocks, as per
the integration guidelines so that MMU isolation can be provided on a
64kB boundary.

Funnily enough, all it takes is to adjust GICC region. You can either:

- make it 128kB wide, and the driver will take care of it (details in
  gic_check_eoimode()). On one of my boxes that is similarly
  configured, I get:

  [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
  [    0.000000] GIC: Adjusting CPU interface base to 0x00000000780af000
  [    0.000000] Root IRQ handler: gic_handle_irq
  [    0.000000] GIC: Using split EOI/Deactivate mode

  See below for what I expect to be the correct fix.
  
- make it 8kB wide from offset 0xF000.

Unless the ST HW folks have been even more creative, none of this
overly complicated stuff should be necessary. Just describe the HW
correctly.

	M.

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index f3c6cdfd7008..97b7a7106a02 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -120,7 +120,7 @@ intc: interrupt-controller@...00000 {
 		#address-cells = <1>;
 		interrupt-controller;
 		reg = <0x0 0x4ac10000 0x0 0x1000>,
-		      <0x0 0x4ac20000 0x0 0x2000>,
+		      <0x0 0x4ac20000 0x0 0x20000>,
 		      <0x0 0x4ac40000 0x0 0x2000>,
 		      <0x0 0x4ac60000 0x0 0x2000>;
 	};

-- 
Jazz isn't dead. It just smells funny.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ