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Message-ID: <20250403122805.1574086-1-christian.bruel@foss.st.com>
Date: Thu, 3 Apr 2025 14:28:02 +0200
From: Christian Bruel <christian.bruel@...s.st.com>
To: <maz@...nel.org>, <tglx@...utronix.de>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<mcoquelin.stm32@...il.com>, <alexandre.torgue@...s.st.com>
CC: <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
Christian Bruel <christian.bruel@...s.st.com>
Subject: [PATCH 0/3] Add ST STM32MP2 GICv2 quirk for EOI split mode
When using GIC EOI split mode, GICC_DIR fails to deactivate the interrupt,
leading to a WFI freeze. On ST MP2, GIC cpu interface is limitted to 4K,
thus GICC_DIR register is reachable with a 0x10000 remapping
When using GIC EOI split mode, the GICC_DIR fails to deactivate the
interrupt, causing core freeze on WFI. On the ST MP2, the GIC CPU interface
is limited to 4K, so the GICC_DIR register can be accessed remapping the
register to a 0x10000 offset.
Christian Bruel (3):
dt-bindings: interrupt-controller: arm,gic: Add
st,stm32mp2-cortex-a7-gic
irqchip/gic: Use 0x10000 offset to access GICC_DIR
arm64: dts: st: add st,stm32mp2-cortex-a7-gic in intc node in
stm32mp251.dtsi
.../interrupt-controller/arm,gic.yaml | 1 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 2 +-
drivers/irqchip/irq-gic.c | 47 ++++++++++++++++++-
3 files changed, 48 insertions(+), 2 deletions(-)
--
2.34.1
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