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Message-ID: <cb07335e-8dc0-4cf1-8524-40770d5419cc@bootlin.com>
Date: Fri, 4 Apr 2025 15:11:00 +0200
From: Thomas Richard <thomas.richard@...tlin.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Bartosz Golaszewski <brgl@...ev.pl>, Lee Jones <lee@...nel.org>,
Pavel Machek <pavel@....cz>, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-leds@...r.kernel.org,
thomas.petazzoni@...tlin.com, DanieleCleri@...on.eu, GaryWang@...on.com.tw
Subject: Re: [PATCH 4/5] pinctrl: Add pin controller driver for AAEON UP
boards
Hi Andy,
On 2/5/25 12:41, Andy Shevchenko wrote:
> On Wed, Feb 05, 2025 at 12:17:29PM +0100, Thomas Richard wrote:
>> On 1/16/25 15:14, Andy Shevchenko wrote:
>
> ...
>
>> So I'm not really convinced by all this complexity for only one driver.
>
> I am not sure if I asked you to show the excerpt from DSDT for this device.
> Is there any link I can browse the ASL code (for that particular device,
> most likely I wouldn't need the full DSDT)?
>
I'm currently working on the V3, and I just remembered that you asked me
DSDT file. So for the UP Squared board, please find the full DSDT, and
also SSDT1 (which contains the FPGA declaration).
DSDT: https://gist.github.com/thom24/4d24c2a2f58d93f799e512c2485efd45
SSDT1: https://gist.github.com/thom24/2da44ef86eacfa5d2d492ce43fa41aa4
Best Regards,
Thomas
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