linux-kernel - [PATCH 2/7] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY

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Message-Id: <20250407-b4-k1-usb3-v3-2-v1-2-bf0bcc41c9ba@whut.edu.cn>
Date: Mon, 07 Apr 2025 20:38:47 +0800
From: Ze Huang <huangze@...t.edu.cn>
To: Vinod Koul <vkoul@...nel.org>, 
 Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Yixun Lan <dlan@...too.org>, 
 Ze Huang <huangze@...t.edu.cn>, 
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
 Philipp Zabel <p.zabel@...gutronix.de>, 
 Thinh Nguyen <Thinh.Nguyen@...opsys.com>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, 
 linux-riscv@...ts.infradead.org, spacemit@...ts.linux.dev, 
 linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org
Subject: [PATCH 2/7] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY

Introduce support for SpacemiT K1 PCIe/USB3 combo PHY controller.

PCIe portA and USB3 controller share this phy, only one of them can work
at any given application scenario.

Signed-off-by: Ze Huang <huangze@...t.edu.cn>
---
 .../bindings/phy/spacemit,k1-combphy.yaml          | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..450157b65410b27129603ea1f3523776a1b0a75e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spacemit K1 PCIe/USB3 PHY
+
+maintainers:
+  - Ze Huang <huangze@...t.edu.cn>
+
+description:
+  Combo PHY on SpacemiT K1 SoC.PCIe port A and USB3 controller share this
+  phy, only one of PCIe port A and USB3 port can work at any given application
+  scenario.
+
+properties:
+  compatible:
+    const: spacemit,k1-combphy
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: phy_ctrl
+      - const: phy_sel
+
+  resets:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    phy@...10000 {
+        compatible = "spacemit,k1-combphy";
+        reg = <0xc0b10000 0x800>,
+              <0xd4282910 0x400>;
+        reg-names = "phy_ctrl", "phy_sel";
+        resets = <&syscon_apmu 19>;
+        #phy-cells = <1>;
+    };

-- 
2.49.0