linux-kernel - Re: [PATCH 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache

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Message-ID: <174403555555.2295519.2830969748366451702.robh@kernel.org>
Date: Mon, 7 Apr 2025 09:19:16 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Ben Zong-You Xie <ben717@...estech.com>
Cc: linux-riscv@...ts.infradead.org, krzk+dt@...nel.org,
	devicetree@...r.kernel.org, tim609@...estech.com,
	palmer@...belt.com, paul.walmsley@...ive.com,
	prabhakar.mahadev-lad.rj@...renesas.com,
	linux-kernel@...r.kernel.org, tglx@...utronix.de,
	aou@...s.berkeley.edu, daniel.lezcano@...aro.org,
	conor+dt@...nel.org, alex@...ti.fr
Subject: Re: [PATCH 6/9] dt-bindings: cache: ax45mp-cache: allow variable
 cache-sets for Andes L2 cache


On Mon, 07 Apr 2025 18:49:34 +0800, Ben Zong-You Xie wrote:
> The current device tree binding for the Andes AX45MP L2 cache enforces
> a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
> the QiLai SoC. This change allows both 1024 and 2048 as valid values for
> "cache-sets".
> 
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> ---
>  .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml       | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@...nel.org>