linux-kernel - Re: [PATCH v3 13/17] x86/apic: Handle EOI writes for SAVIC guests

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Message-ID: <Z_PzDyiyLGq2tJl8@google.com>
Date: Mon, 7 Apr 2025 08:45:19 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, tglx@...utronix.de, 
	mingo@...hat.com, dave.hansen@...ux.intel.com, Thomas.Lendacky@....com, 
	nikunj@....com, Santosh.Shukla@....com, Vasant.Hegde@....com, 
	Suravee.Suthikulpanit@....com, David.Kaplan@....com, x86@...nel.org, 
	hpa@...or.com, peterz@...radead.org, pbonzini@...hat.com, kvm@...r.kernel.org, 
	kirill.shutemov@...ux.intel.com, huibo.wang@....com, naveen.rao@....com, 
	francescolavra.fl@...il.com
Subject: Re: [PATCH v3 13/17] x86/apic: Handle EOI writes for SAVIC guests

On Tue, Apr 01, 2025, Neeraj Upadhyay wrote:
> Secure AVIC accelerates guest's EOI msr writes for edge-triggered
> interrupts. For level-triggered interrupts, EOI msr writes trigger
> VC exception with SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. The
> VC handler would need to trigger a GHCB protocol MSR write event to
> to notify the Hypervisor about completion of the level-triggered
> interrupt. This is required for cases like emulated IOAPIC. VC exception
> handling adds extra performance overhead for APIC register write. In
> addition, some unaccelerated APIC register msr writes are trapped,
> whereas others are faulted. This results in additional complexity in
> VC exception handling for unacclerated accesses. So, directly do a GHCB
> protocol based EOI write from apic->eoi() callback for level-triggered
> interrupts. Use wrmsr for edge-triggered interrupts, so that hardware
> re-evaluates any pending interrupt which can be delivered to guest vCPU.
> For level-triggered interrupts, re-evaluation happens on return from
> VMGEXIT corresponding to the GHCB event for EOI msr write.
> 
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
> ---
> Changes since v2:
>  - Reuse find_highest_vector() from kvm/lapic.c
>  - Misc cleanups.
> 
>  arch/x86/include/asm/apic-emul.h    | 28 +++++++++++++
>  arch/x86/kernel/apic/x2apic_savic.c | 62 +++++++++++++++++++++++++----
>  arch/x86/kvm/lapic.c                | 23 ++---------

Please isolate the KVM changes to a standalone patch.

>  3 files changed, 85 insertions(+), 28 deletions(-)
>  create mode 100644 arch/x86/include/asm/apic-emul.h
> 
> diff --git a/arch/x86/include/asm/apic-emul.h b/arch/x86/include/asm/apic-emul.h
> new file mode 100644
> index 000000000000..60d9e88fefc6
> --- /dev/null
> +++ b/arch/x86/include/asm/apic-emul.h

I don't see any reason for a new file.  arch/x86/include/asm/apic.h already has
is_vector_pending() and lapic_vector_set_in_irr(), this functionality is more or
less the same.