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Message-ID: <3fdfd450-6624-4621-bcae-5457da7cacc7@linux.dev>
Date: Mon, 7 Apr 2025 22:50:09 +0530
From: Aradhya Bhatia <aradhya.bhatia@...ux.dev>
To: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>,
Jyri Sarha <jyri.sarha@....fi>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>
Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, Francesco Dolcini <francesco@...cini.it>,
Devarsh Thakkar <devarsht@...com>
Subject: Re: [PATCH v2 03/18] drm/tidss: Adjust the pclk based on the HW
capabilities
On 02/04/25 19:00, Tomi Valkeinen wrote:
> At the moment the driver just sets the clock rate with clk_set_rate(),
> and if the resulting rate is not the same as requested, prints a debug
> print, but nothing else.
>
> Add functionality to atomic_check(), in which the clk_round_rate() is
> used to get the "rounded" rate, and set that to the adjusted_mode.
>
> In practice, with the current K3 SoCs, the display PLL is capable of
> producing very exact clocks, so most likely the rounded rate is the same
> as the original one.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
> ---
> drivers/gpu/drm/tidss/tidss_crtc.c | 23 +++++++++++++++++++----
> drivers/gpu/drm/tidss/tidss_dispc.c | 6 ++++++
> drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++
> 3 files changed, 27 insertions(+), 4 deletions(-)
>
Reviewed-by: Aradhya Bhatia <aradhya.bhatia@...ux.dev>
--
Regards
Aradhya
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