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Message-ID: <20250407172836.1009461-1-ivecera@redhat.com>
Date: Mon, 7 Apr 2025 19:28:27 +0200
From: Ivan Vecera <ivecera@...hat.com>
To: netdev@...r.kernel.org
Cc: Vadim Fedorenko <vadim.fedorenko@...ux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
Jiri Pirko <jiri@...nulli.us>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Prathosh Satish <Prathosh.Satish@...rochip.com>,
Lee Jones <lee@...nel.org>,
Kees Cook <kees@...nel.org>,
Andy Shevchenko <andy@...nel.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Michal Schmidt <mschmidt@...hat.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-hardening@...r.kernel.org
Subject: [PATCH 00/28] Add Microchip ZL3073x support
This series adds support for Microchip Azurite DPLL/PTP/SyncE chip
family. These chips provide DPLL and PTP functionality, so the series
adds the common MFD driver that provides an access to the bus that can
be either I2C or SPI. The second part of the series is DPLL driver that
covers DPLL functionality. The PTP support will be added by separate
series as well as flashing capability.
All functionality was tested by myself and by Prathosh Satish on
Microchip EDS2 development board with ZL30732 DPLL chip connected over
I2C bus.
Patch breakdown
===============
Patch 1 - Basic support for I2C, SPI and regmap
Patch 2 - Devlink registration
Patches 3-4 - Helpers for accessing device registers
Patches 5-6 - Component versions reporting via devlink dev info
Patches 7-8 - Helpers for accessing register mailboxes
Patch 9 - Clock ID generation for DPLL driver
Patch 10 - Export strnchrnul function for modules
(used by next patch)
Patch 11 - Support for MFG config initialization file
Patch 12 - Fetch invariant register values used by DPLL and later by
PTP driver
Patch 13 - Basic DPLL driver with required only functionality
Patch 14 - Registration of DPLL sub-devices by MFD driver
Patch 15 - Device tree bindings for DPLL device and pin
Patch 16 - Device tree bindings for ZL3073x device
Patch 17 - Read DPLL device types from firmware (DT,ACPI...)
Patch 18 - Read basic pin properties from firmware
Patch 19 - Implementation of input pin selection for DPLL in manual mode
Patch 20 - Implementation of getting/setting priority for input pins
Patch 21 - Implementation of input pin state setting for DPLL in auto mode
Patch 22 - Implementation of getting/setting frequency for input pins
Patch 23 - Implementation of getting/setting frequency for output pins
Patch 24 - Read pin supported frequencies from firmware
Patch 25 - Implementation of getting phase offset from input pins
Patch 26 - Implementation of getting/setting phase adjust for both
pin types
Patch 27 - Implementation of getting/setting embedded sync frequency
for both pin types
Patch 28 - Implementation of getting fractional frequency offset for
input pins
Ivan Vecera (28):
mfd: Add Microchip ZL3073x support
mfd: zl3073x: Register itself as devlink device
mfd: zl3073x: Add register access helpers
mfd: zl3073x: Add macros for device registers access
mfd: zl3073x: Add components versions register defs
mfd: zl3073x: Implement devlink device info
mfd: zl3073x: Add macro to wait for register value bits to be cleared
mfd: zl3073x: Add functions to work with register mailboxes
mfd: zl3073x: Add clock_id field
lib: Allow modules to use strnchrnul
mfd: zl3073x: Load mfg file into HW if it is present
mfd: zl3073x: Fetch invariants during probe
dpll: Add Microchip ZL3073x DPLL driver
mfd: zl3073x: Register DPLL sub-device during init
dt-bindings: dpll: Add device tree bindings for DPLL device and pin
dt-bindings: dpll: Add support for Microchip Azurite chip family
dpll: zl3073x: Read DPLL types from firmware
dpll: zl3073x: Read optional pin properties from firmware
dpll: zl3073x: Implement input pin selection in manual mode
dpll: zl3073x: Add support to get/set priority on input pins
dpll: zl3073x: Implement input pin state setting in automatic mode
dpll: zl3073x: Add support to get/set frequency on input pins
dpll: zl3073x: Add support to get/set frequency on output pins
dpll: zl3073x: Read pin supported frequencies from firmware
dpll: zl3073x: Add support to get phase offset on input pins
dpll: zl3073x: Add support to get/set phase adjust on pins
dpll: zl3073x: Add support to get/set esync on pins
dpll: zl3073x: Add support to get fractional frequency offset on input
pins
.../devicetree/bindings/dpll/dpll-device.yaml | 84 +
.../devicetree/bindings/dpll/dpll-pin.yaml | 43 +
.../bindings/dpll/microchip,zl3073x.yaml | 74 +
MAINTAINERS | 12 +
drivers/dpll/Kconfig | 16 +
drivers/dpll/Makefile | 2 +
drivers/dpll/dpll_zl3073x.c | 2768 +++++++++++++++++
drivers/mfd/Kconfig | 33 +
drivers/mfd/Makefile | 5 +
drivers/mfd/zl3073x-core.c | 840 +++++
drivers/mfd/zl3073x-i2c.c | 71 +
drivers/mfd/zl3073x-spi.c | 72 +
drivers/mfd/zl3073x.h | 13 +
include/linux/mfd/zl3073x.h | 335 ++
lib/string.c | 1 +
15 files changed, 4369 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml
create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml
create mode 100644 Documentation/devicetree/bindings/dpll/microchip,zl3073x.yaml
create mode 100644 drivers/dpll/dpll_zl3073x.c
create mode 100644 drivers/mfd/zl3073x-core.c
create mode 100644 drivers/mfd/zl3073x-i2c.c
create mode 100644 drivers/mfd/zl3073x-spi.c
create mode 100644 drivers/mfd/zl3073x.h
create mode 100644 include/linux/mfd/zl3073x.h
--
2.48.1
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