linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

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Message-ID: <3ab630f4-8b1e-46ea-a8c6-a2878cfff78b@linaro.org>
Date: Mon, 7 Apr 2025 09:21:19 +0200
From: neil.armstrong@...aro.org
To: Pengyu Luo <mitltlatltl@...il.com>, Bjorn Andersson
 <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

On 05/04/2025 12:55, Pengyu Luo wrote:
> Only two little a520s share the same L2, every a720 has their own L2
> cache.
> 
> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
> Signed-off-by: Pengyu Luo <mitltlatltl@...il.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index a2b3d97ab..f47f29ec8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -187,7 +187,7 @@ cpu3: cpu@300 {
>   			power-domain-names = "psci";
>   
>   			enable-method = "psci";
> -			next-level-cache = <&l2_200>;
> +			next-level-cache = <&l2_300>;
>   			capacity-dmips-mhz = <1792>;
>   			dynamic-power-coefficient = <238>;
>   
> @@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
>   					 &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   
>   			#cooling-cells = <2>;
> +
> +			l2_300: l2-cache {
> +				compatible = "cache";
> +				cache-level = <2>;
> +				cache-unified;
> +				next-level-cache = <&l3_0>;
> +			};
>   		};
>   
>   		cpu4: cpu@400 {

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>