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Message-ID: <c14389a1-1904-450f-98c5-a55351518ed7@linaro.org>
Date: Mon, 7 Apr 2025 09:37:56 +0200
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>, tglx@...utronix.de
Cc: linux-kernel@...r.kernel.org, thomas.fossati@...aro.org,
Larisa.Grigore@....com, ghennadi.procopciuc@....com,
krzysztof.kozlowski@...aro.org, S32@....com, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
"moderated list:ARM/STM32 ARCHITECTURE"
<linux-stm32@...md-mailman.stormreply.com>,
"moderated list:ARM/STM32 ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v4 1/2] dt-bindings: timer: Add NXP System Timer Module
On 03/04/2025 17:21, Daniel Lezcano wrote:
> On 03/04/2025 08:33, Ghennadi Procopciuc wrote:
>> On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
>> [ ... ]
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> + timer@...1c000 {
>>> + compatible = "nxp,s32g2-stm";
>>> + reg = <0x4011c000 0x3000>;
>>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clks 0x3b>;
>>> + };
>>
>> The S32G reference manual specifies two clocks for the STM module: one
>> for the registers and another for the counter itself. Shouldn't both
>> clocks be represented in the bindings?
>
> AFAICS, there are two clocks as described in the documentation for the
> s32g2 page 843, section 23.7.3 Timer modules.
>
> The module and the register clock are fed by the XBAR_DIV3_CLK which is
> an system clock always-on.
>
> page 1994, 40.5.4 Clocking, the documentation says: "This module has no
> clocking considerations."
>
> From my understanding, we should not describe the XBAR_DIV3_CLK as it
> is a system clock.
Can you clarify for the STM if you still want to change the binding ?
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