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Message-ID: <cfd77ff7-8dae-4994-affb-d2cdaaace33a@fujitsu.com>
Date: Mon, 7 Apr 2025 01:52:40 +0000
From: "Zhijian Li (Fujitsu)" <lizhijian@...itsu.com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
CC: Dan Williams <dan.j.williams@...el.com>, Ira Weiny <ira.weiny@...el.com>,
"linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>, Dave Jiang
<dave.jiang@...el.com>, Alison Schofield <alison.schofield@...el.com>, Vishal
Verma <vishal.l.verma@...el.com>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] cxl/acpi: Verify CHBS length for CXL2.0
On 04/04/2025 21:53, Jonathan Cameron wrote:
>> While the immediate impact might be limited to edge cases (e.g., incorrect QEMU configurations),
>> upstreaming this aligns the kernel with spec-mandated checks and improves
>> robustness for future use cases.
>>
>> [1]https://cdrdv2-public.intel.com/643805/643805_CXL_Memory_Device_SW_Guide_Rev1_1.pdf
> Just to check - are we talking hacked QEMU or some configuration of QEMU that
> can generate the wrong length?
A hacked QEMU.
>
> Jonathan
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