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Message-ID: <CAAyq3SYUjyXCPqfiXi=dRNkicf9osxMrZ3Mf2-eHJVMUDnRs5g@mail.gmail.com>
Date: Mon, 7 Apr 2025 16:25:39 +0800
From: Cheng Ming Lin <linchengming884@...il.com>
To: tudor.ambarus@...aro.org, pratyush@...nel.org, mwalle@...nel.org,
miquel.raynal@...tlin.com, richard@....at, vigneshr@...com,
linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: alvinzhou@...c.com.tw, leoyu@...c.com.tw,
Cheng Ming Lin <chengminglin@...c.com.tw>
Subject: Re: [PATCH v2 3/3] mtd: spi-nor: macronix: Add fixups for MX25L3255E
Sorry for missing the minimum testing requirements.
Here are the details:
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c29e16
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> hexdump -Cv /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
00000000 53 46 44 50 00 01 01 ff 00 00 01 09 30 00 00 ff |SFDP........0...|
00000010 c2 00 01 04 60 00 00 ff ff ff ff ff ff ff ff ff |....`...........|
00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000030 e5 20 f1 ff ff ff ff 01 44 eb 08 6b 08 3b 04 bb |. ......D..k.;..|
00000040 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 |............. .R|
00000050 10 d8 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000060 00 36 00 27 9e 49 ff ff d9 f8 ff ff ff ff ff ff |.6.'.I..........|
00000070
zynq> sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
cf7b2e5b00388040786877de15f7594fcc064a1b7dbe34393a06d462cc1da9b0
/sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 0
dummy cycles 4
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-4S-4S
opcode 0x38
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 9e 16 c2 9e 16
size 4.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_16BIT_SR
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x38
8D extension none
protocols
read 1S-4S-4S
write 1S-4S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (4.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+----------
00000000-003fffff | [ 3] | no
zynq> dd if=/dev/urandom of=/tmp/spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.084038 seconds, 23.8MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 /tmp/spi_read
Copied 2097152 bytes from address 0x00000000 in flash to /tmp/spi_read
zynq> hexdump /tmp/spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum /tmp/spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 /tmp/spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 /tmp/spi_test
Copied 2097152 bytes from /tmp/spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 /tmp/spi_read
Copied 2097152 bytes from address 0x00000000 in flash to /tmp/spi_read
zynq> sha256sum /tmp/spi*
0be542d171336e052532d4b4f50b148293f7436f640211644df075da8682f54a /tmp/spi_read
0be542d171336e052532d4b4f50b148293f7436f640211644df075da8682f54a /tmp/spi_test
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 /tmp/spi_read
Copied 2097152 bytes from address 0x00000000 in flash to /tmp/spi_read
zynq> sha256sum /tmp/spi*
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 /tmp/spi_read
0be542d171336e052532d4b4f50b148293f7436f640211644df075da8682f54a /tmp/spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 4194304 (4M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
Cheng Ming Lin <linchengming884@...il.com> 於 2025年4月7日 週一 下午3:59寫道：
>
> From: Cheng Ming Lin <chengminglin@...c.com.tw>
>
> SFDP of MX25L3255E is JESD216, which does not include the Quad
> Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> Therefore, it is necessary to correct this setting by late_init.
>
> In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> address mode. However, since the 3-byte address 1-4-4 page program
> is not defined in SFDP, it needs to be configured in late_init.
>
> Signed-off-by: Cheng Ming Lin <chengminglin@...c.com.tw>
> ---
> drivers/mtd/spi-nor/macronix.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 07e0bd0b70a0..4bbd3b651cec 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
> return 0;
> }
>
> +static int
> +mx25l3255e_late_init_fixups(struct spi_nor *nor)
> +{
> + /*
> + * SFDP of MX25L3255E is JESD216, which does not include the Quad
> + * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> + * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> + * Therefore, it is necessary to correct this setting by late_init.
> + */
> + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> +
> + /*
> + * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> + * address mode. However, since the 3-byte address 1-4-4 page program
> + * is not defined in SFDP, it needs to be configured in late_init.
> + */
> + struct spi_nor_flash_parameter *params = nor->params;
> +
> + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
> + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4],
> + SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);
> +
> + return 0;
> +}
> +
> static const struct spi_nor_fixups mx25l25635_fixups = {
> .post_bfpt = mx25l25635_post_bfpt_fixups,
> .post_sfdp = macronix_qpp4b_post_sfdp_fixups,
> @@ -67,6 +92,10 @@ static const struct spi_nor_fixups macronix_qpp4b_fixups = {
> .post_sfdp = macronix_qpp4b_post_sfdp_fixups,
> };
>
> +static const struct spi_nor_fixups mx25l3255e_fixups = {
> + .late_init = mx25l3255e_late_init_fixups,
> +};
> +
> static const struct flash_info macronix_nor_parts[] = {
> {
> .id = SNOR_ID(0xc2, 0x20, 0x10),
> @@ -199,6 +228,7 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25L3255E */
> .id = SNOR_ID(0xc2, 0x9e, 0x16),
> + .fixups = &mx25l3255e_fixups,
> },
> /*
> * This spares us of adding new flash entries for flashes that can be
> --
> 2.25.1
>
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