| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <6ccfc126-b009-4ee9-0a2c-3e7faf512751@rock-chips.com>
Date: Tue, 8 Apr 2025 11:01:04 +0800
From: Shawn Lin <shawn.lin@...k-chips.com>
To: Kever Yang <kever.yang@...k-chips.com>, heiko@...ech.de
Cc: shawn.lin@...k-chips.com, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org, Conor Dooley <conor+dt@...nel.org>,
Finley Xiao <finley.xiao@...k-chips.com>,
Frank Wang <frank.wang@...k-chips.com>, Rob Herring <robh@...nel.org>,
Liang Chen <cl@...k-chips.com>,
Detlev Casanova <detlev.casanova@...labora.com>,
linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Yifeng Zhao <yifeng.zhao@...k-chips.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes
在 2025/02/25 星期二 18:26, Kever Yang 写道:
> rk3576 has two pcie controllers, both are pcie2x1 work with
> naneng-combphy.
>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
> ---
>
One thing need to be mentioned, defconfig set:
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=m
So the phy is missing leads deferred probe pending.
With setting CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y,
pcie works fine, so
Tested-by: Shawn Lin <Shawn.lin@...k-chips.com>
> Changes in v7:
> - re-order the properties.
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Update the subject
>
> Changes in v2:
> - Update clock and reset names and sequence to pass DTB check
>
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index 4dde954043ef..79e24b2c3c60 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1127,6 +1127,114 @@ qos_npu_m1ro: qos@...22100 {
> reg = <0x0 0x27f22100 0x0 0x20>;
> };
>
> + pcie0: pcie@...00000 {
> + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
> + reg = <0x0 0x22000000 0x0 0x00400000>,
> + <0x0 0x2a200000 0x0 0x00010000>,
> + <0x0 0x20000000 0x0 0x00100000>;
> + reg-names = "dbi", "apb", "config";
> + bus-range = <0x0 0xf>;
> + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
> + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
> + <&cru CLK_PCIE0_AUX>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux";
> + device_type = "pci";
> + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie0_intc 0>,
> + <0 0 0 2 &pcie0_intc 1>,
> + <0 0 0 3 &pcie0_intc 2>,
> + <0 0 0 4 &pcie0_intc 3>;
> + linux,pci-domain = <0>;
> + max-link-speed = <2>;
> + num-ib-windows = <8>;
> + num-viewport = <8>;
> + num-ob-windows = <2>;
> + num-lanes = <1>;
> + phys = <&combphy0_ps PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3576_PD_PHP>;
> + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
> + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
> + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
> + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> + reset-names = "pwr", "pipe";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + pcie0_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> + pcie1: pcie@...10000 {
> + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
> + reg = <0x0 0x22400000 0x0 0x00400000>,
> + <0x0 0x2a210000 0x0 0x00010000>,
> + <0x0 0x21000000 0x0 0x00100000>;
> + reg-names = "dbi", "apb", "config";
> + bus-range = <0x20 0x2f>;
> + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
> + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
> + <&cru CLK_PCIE1_AUX>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux";
> + device_type = "pci";
> + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> + <0 0 0 2 &pcie1_intc 1>,
> + <0 0 0 3 &pcie1_intc 2>,
> + <0 0 0 4 &pcie1_intc 3>;
> + linux,pci-domain = <0>;
> + max-link-speed = <2>;
> + num-ib-windows = <8>;
> + num-viewport = <8>;
> + num-ob-windows = <2>;
> + num-lanes = <1>;
> + phys = <&combphy1_psu PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3576_PD_SUBPHP>;
> + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
> + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
> + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
> + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> + reset-names = "pwr", "pipe";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + pcie1_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> gmac0: ethernet@...20000 {
> compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
> reg = <0x0 0x2a220000 0x0 0x10000>;
Powered by blists - more mailing lists