linux-kernel - Re: [PATCH v4 4/8] clocksource: stm32-lptimer: add support for stm32mp25

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <d66bd978-820a-4700-92c2-ba52d7db4efb@foss.st.com>
Date: Tue, 8 Apr 2025 16:48:50 +0200
From: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
To: <lee@...nel.org>, <alexandre.torgue@...s.st.com>,
        <daniel.lezcano@...aro.org>, <tglx@...utronix.de>
CC: <krzk+dt@...nel.org>, <jic23@...nel.org>, <conor+dt@...nel.org>,
        <ukleinek@...nel.org>, <robh@...nel.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <devicetree@...r.kernel.org>, <wbg@...nel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-iio@...r.kernel.org>, <linux-pwm@...r.kernel.org>,
        <olivier.moysan@...s.st.com>
Subject: Re: [PATCH v4 4/8] clocksource: stm32-lptimer: add support for
 stm32mp25

On 3/14/25 18:14, Fabrice Gasnier wrote:
> On stm32mp25, DIER (former IER) must only be modified when the lptimer
> is enabled. On earlier SoCs, it must be only be modified when it is
> disabled. There's also a new DIEROK flag, to ensure register access
> has completed.
> Add a new "set_evt" routine to be used on stm32mp25, called depending
> on the version register, read by the MFD core (LPTIM_VERR).
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@...s.st.com>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
> ---
> Changes in V4:
> - Daniel suggests to encapsulate IER write into a separate function
>   that manages the enabling/disabling of the LP timer. In addition,
>   DIEROK and ARROK flags checks have been added. So adopt a new routine
>   to set the event into ARR register and enable the interrupt.

Hi all, Daniel,

Does anybody else have additional remarks on this driver ?

I think Lee is waiting for review, before merging the MFD part (at least).

Best Regards,
Thanks,
Fabrice

> Changes in V2:
> - rely on fallback compatible as no specific .data is associated to the
>   driver. Use version data from MFD core.
> - Added interrupt enable register access update in (missed in V1)
> ---
>  drivers/clocksource/timer-stm32-lp.c | 51 +++++++++++++++++++++++++---
>  1 file changed, 47 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/timer-stm32-lp.c
> index 928da2f6de69..e58932300fb4 100644
> --- a/drivers/clocksource/timer-stm32-lp.c
> +++ b/drivers/clocksource/timer-stm32-lp.c
> @@ -27,6 +27,7 @@ struct stm32_lp_private {
>  	u32 psc;
>  	struct device *dev;
>  	struct clk *clk;
> +	u32 version;
>  };
>  
>  static struct stm32_lp_private*
> @@ -47,12 +48,37 @@ static int stm32_clkevent_lp_shutdown(struct clock_event_device *clkevt)
>  	return 0;
>  }
>  
> -static int stm32_clkevent_lp_set_timer(unsigned long evt,
> -				       struct clock_event_device *clkevt,
> -				       int is_periodic)
> +static int stm32mp25_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt)
>  {
> -	struct stm32_lp_private *priv = to_priv(clkevt);
> +	int ret;
> +	u32 val;
> +
> +	/* Enable LPTIMER to be able to write into IER and ARR registers */
> +	regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
> +	/* set next event counter */
> +	regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
> +	/* enable ARR interrupt */
> +	regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
> +
> +	/* Poll DIEROK and ARROK to ensure register access has completed */
> +	ret = regmap_read_poll_timeout_atomic(priv->reg, STM32_LPTIM_ISR, val,
> +					      (val & STM32_LPTIM_DIEROK_ARROK) ==
> +					      STM32_LPTIM_DIEROK_ARROK,
> +					      10, 500);
> +	if (ret) {
> +		dev_err(priv->dev, "access to LPTIM timed out\n");
> +		/* Disable LPTIMER */
> +		regmap_write(priv->reg, STM32_LPTIM_CR, 0);
> +		return ret;
> +	}
> +	/* Clear DIEROK and ARROK flags */
> +	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_DIEROKCF_ARROKCF);
> +
> +	return 0;
> +}
>  
> +static void stm32_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt)
> +{
>  	/* disable LPTIMER to be able to write into IER register*/
>  	regmap_write(priv->reg, STM32_LPTIM_CR, 0);
>  	/* enable ARR interrupt */
> @@ -61,6 +87,22 @@ static int stm32_clkevent_lp_set_timer(unsigned long evt,
>  	regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
>  	/* set next event counter */
>  	regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
> +}
> +
> +static int stm32_clkevent_lp_set_timer(unsigned long evt,
> +				       struct clock_event_device *clkevt,
> +				       int is_periodic)
> +{
> +	struct stm32_lp_private *priv = to_priv(clkevt);
> +	int ret;
> +
> +	if (priv->version == STM32_LPTIM_VERR_23) {
> +		ret = stm32mp25_clkevent_lp_set_evt(priv, evt);
> +		if (ret)
> +			return ret;
> +	} else {
> +		stm32_clkevent_lp_set_evt(priv, evt);
> +	}
>  
>  	/* start counter */
>  	if (is_periodic)
> @@ -176,6 +218,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	priv->reg = ddata->regmap;
> +	priv->version = ddata->version;
>  	priv->clk = ddata->clk;
>  	ret = clk_prepare_enable(priv->clk);
>  	if (ret)