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Message-ID: <ed9880a0-0dd5-4ae0-a9d0-d871fae200ac@fujitsu.com>
Date: Tue, 8 Apr 2025 05:37:16 +0000
From: "Zhijian Li (Fujitsu)" <lizhijian@...itsu.com>
To: Gregory Price <gourry@...rry.net>
CC: "lsf-pc@...ts.linux-foundation.org" <lsf-pc@...ts.linux-foundation.org>,
"linux-mm@...ck.org" <linux-mm@...ck.org>, "linux-cxl@...r.kernel.org"
<linux-cxl@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: Re: CXL Boot to Bash - Section 2a (Drivers): CXL Decoder Programming
Gregory,
On 08/04/2025 12:14, Gregory Price wrote:
> My reading of the 3.1 spec suggests this is also defined by implication
> of the "Implementation Notes" at the end of section
>
> 8.2.4.20 CXL HDM Decoder Capability Structure
>
> IMPLEMENTATION NOTE
> CXL Host Bridge and Upstream Switch Port Decode Flow
>
> IMPLEMENTATION NOTE
> Device Decode Logic
Great, I am grateful for your enlightening guidance.
Many many thanks again.
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