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Message-ID: <20250409232713.4536-1-chang.seok.bae@intel.com>
Date: Wed, 9 Apr 2025 16:27:07 -0700
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: linux-kernel@...r.kernel.org
Cc: x86@...nel.org,
tglx@...utronix.de,
mingo@...hat.com,
bp@...en8.de,
dave.hansen@...ux.intel.com,
colinmitchell@...gle.com,
chao.gao@...el.com,
chang.seok.bae@...el.com
Subject: [PATCH v3 0/6] x86: Support for Intel Microcode Staging Feature
Hi all,
This is another revision addressing feedback from the last posting [1]
over the past few weeks:
* Dave suggested using a local variable to clarify the scope handled
by each helper, via a function argument [2]. Accordingly, the patch
order was adjusted (patch 2 <-> patch 3).
* Chao provided helpful feedback, leading to additional refinements.
This round contains relatively smaller changes compared to the last one,
but I hope this iteration provide a chance to draw more reviews or even
collect a few tags.
As before, the patch series is based on tip/master and is also available
in this repo:
git://github.com/intel-staging/microcode.git staging_v3
Thanks,
Chang
[1]: V2: https://lore.kernel.org/lkml/Z+O8DK5NZJL43Nt6@intel.com/
[2]: https://lore.kernel.org/lkml/b01224ee-c935-4b08-a76f-5dc49341182d@intel.com/
Chang S. Bae (6):
x86/microcode: Introduce staging step to reduce late-loading time
x86/microcode/intel: Establish staging control logic
x86/microcode/intel: Define staging state struct
x86/microcode/intel: Implement staging handler
x86/microcode/intel: Support mailbox transfer
x86/microcode/intel: Enable staging when available
arch/x86/include/asm/msr-index.h | 9 +
arch/x86/include/asm/topology.h | 1 +
arch/x86/kernel/cpu/microcode/core.c | 11 +
arch/x86/kernel/cpu/microcode/intel.c | 338 +++++++++++++++++++++++
arch/x86/kernel/cpu/microcode/internal.h | 4 +-
5 files changed, 362 insertions(+), 1 deletion(-)
base-commit: 033163360247053bec75b81ac2d34aeb9d994e59
--
2.45.2
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