linux-kernel - Re: [PATCH v4 1/2] dt-bindings: memory-controllers: Add MediaTek DRAM controller interface

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f26c71f4-3a17-4335-943c-90e3671c9266@kernel.org>
Date: Wed, 9 Apr 2025 09:33:39 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Crystal Guo (郭晶) <Crystal.Guo@...iatek.com>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "conor+dt@...nel.org" <conor+dt@...nel.org>,
 Project_Global_Chrome_Upstream_Group
 <Project_Global_Chrome_Upstream_Group@...iatek.com>,
 "robh@...nel.org" <robh@...nel.org>,
 "linux-arm-kernel@...ts.infradead.org"
 <linux-arm-kernel@...ts.infradead.org>,
 "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Subject: Re: [PATCH v4 1/2] dt-bindings: memory-controllers: Add MediaTek DRAM
 controller interface

On 09/04/2025 09:16, Crystal Guo (郭晶) wrote:
> On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
>>> +maintainers:
>>> +  - Crystal Guo <crystal.guo@...iatek.com>
>>> +
>>> +description:
>>> +  A MediaTek DRAM controller interface to provide the current data
>>> rate of DRAM.
>>
>> DRAM controller does not offer scaling? Or PHY/timing configuration?
>> This binding looks pretty incomplete.
>>
> 
> The PHY/timing configuration is completed during the bootloader stage.
> In the kernel, we currently only need to provide an interface to
> retrieve the current DDR data rate.
Not really, that's what you currently want to do in kernel, but not what
you for example will want next days. Binding is supposed to be complete,
so if you do not have any scaling/interconnect then extend the
description of hardware and explain that memory controller is non
configurable, cannot scale and it exposes only read interface. Or
something similar.

Best regards,
Krzysztof