linux-kernel - Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

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Message-ID: <Z/fV+SP0z+slV9/1@redbud>
Date: Thu, 10 Apr 2025 09:30:17 -0500
From: "Tyler Hicks (Microsoft)" <code@...icks.com>
To: Marc Zyngier <maz@...nel.org>
Cc: Krzysztof Kozlowski <krzk@...nel.org>,
	Vijay Balakrishna <vijayb@...ux.microsoft.com>,
	Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>,
	James Morse <james.morse@....com>,
	Mauro Carvalho Chehab <mchehab@...nel.org>,
	Robert Richter <rric@...nel.org>, linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org, Sascha Hauer <s.hauer@...gutronix.de>
Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

On 2025-04-10 08:10:18, Marc Zyngier wrote:
> On Thu, 10 Apr 2025 07:00:55 +0100,
> Krzysztof Kozlowski <krzk@...nel.org> wrote:
> > 
> > On 10/04/2025 01:36, Vijay Balakrishna wrote:
> > > From: Sascha Hauer <s.hauer@...gutronix.de>
> > > 
> > > Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And
> > > Correction (EDAC) support on their L1 and L2 caches. This is implemented
> > > in implementation defined registers, so usage of this functionality is
> > > not safe in virtualized environments or when EL3 already uses these
> > > registers. This patch adds a edac-enabled flag which can be explicitly
> > > set when EDAC can be used.
> > 
> > Can't hypervisor tell you that?
> 
> No, it can't. This is not an architecture feature, and KVM will gladly
> inject an UNDEF exception if the guest tries to use this.
> 
> Which is yet another reason why this whole exercise is futile.

Hi Marc - could you clarify why this is futile for baremetal or were you just
referring to virtualized environments?

Thanks!

Tyler

> 
> 	M.
> 
> -- 
> Without deviation from the norm, progress is not possible.