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Message-Id: <20250410-dt-cpu-schema-v2-5-63d7dc9ddd0a@kernel.org>
Date: Thu, 10 Apr 2025 10:47:26 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
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Claudiu Beznea <claudiu.beznea@...on.dev>,
Steen Hegelund <Steen.Hegelund@...rochip.com>,
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Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
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Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, imx@...ts.linux.dev,
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linux-renesas-soc@...r.kernel.org, linux-mips@...r.kernel.org,
linux-pm@...r.kernel.org, linux-mediatek@...ts.infradead.org
Subject: [PATCH v2 05/17] arm64: dts: qcom: msm8939: Fix CPU node
"enable-method" property dependencies
The "spin-table" enable-method requires "cpu-release-addr" property,
so add a dummy entry. It is assumed the bootloader will fill in the
correct values.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
---
v2:
- Keep qcom,saw and qcom,acc properties
---
arch/arm64/boot/dts/qcom/msm8939.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index 7cd5660de1b3..72f01953e65c 100644
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -46,6 +46,7 @@ cpu0: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x100>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc0>;
@@ -64,6 +65,7 @@ cpu1: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x101>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc1>;
@@ -77,6 +79,7 @@ cpu2: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x102>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc2>;
@@ -90,6 +93,7 @@ cpu3: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x103>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc3>;
@@ -103,6 +107,7 @@ cpu4: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x0>;
qcom,acc = <&acc4>;
qcom,saw = <&saw4>;
@@ -121,6 +126,7 @@ cpu5: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x1>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc5>;
@@ -134,6 +140,7 @@ cpu6: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x2>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc6>;
@@ -147,6 +154,7 @@ cpu7: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
+ cpu-release-addr = /bits/ 64 <0>;
reg = <0x3>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc7>;
--
2.47.2
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