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Message-Id: <20250410-dt-cpu-schema-v2-15-63d7dc9ddd0a@kernel.org>
Date: Thu, 10 Apr 2025 10:47:36 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>, Conor Dooley <conor@...nel.org>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Claudiu Beznea <claudiu.beznea@...on.dev>,
Steen Hegelund <Steen.Hegelund@...rochip.com>,
Daniel Machon <daniel.machon@...rochip.com>, UNGLinuxDriver@...rochip.com,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Heiko Stuebner <heiko@...ech.de>,
Neil Armstrong <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>, Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Andy Gross <agross@...nel.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>, zhouyanjie@...yeetech.com,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Stephan Gerhold <stephan.gerhold@...aro.org>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, imx@...ts.linux.dev,
linux-rockchip@...ts.infradead.org, linux-amlogic@...ts.infradead.org,
linux-renesas-soc@...r.kernel.org, linux-mips@...r.kernel.org,
linux-pm@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Sudeep Holla <sudeep.holla@....com>, Viresh Kumar <viresh.kumar@...aro.org>
Subject: [PATCH v2 15/17] dt-bindings: arm/cpus: Add missing properties
The Arm CPU schema is missing a number of properties already in use.
This has gone unnoticed as extra properties have not been restricted.
Add a missing reference to cpu.yaml, and add all the missing properties.
As "clock-latency" and "voltage-tolerance" are related to opp-v1, add
those properties to the opp-v1.yaml schema.
With this, other properties can be prevented from creeping in with
'unevaluatedProperties: false'.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Sudeep Holla <sudeep.holla@....com>
Acked-by: Viresh Kumar <viresh.kumar@...aro.org>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 46 ++++++++++++++++++++++-
Documentation/devicetree/bindings/opp/opp-v1.yaml | 16 ++++++++
2 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 5af1396d631f..3846f13ded5b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -299,6 +299,16 @@ properties:
where voltage is in V, frequency is in MHz.
+ interconnects:
+ minItems: 1
+ maxItems: 2
+
+ nvmem-cells:
+ maxItems: 1
+
+ nvmem-cell-names:
+ const: speed_grade
+
performance-domains:
maxItems: 1
@@ -317,6 +327,31 @@ properties:
corresponding to the index of an SCMI performance domain provider, must be
"perf".
+ resets:
+ maxItems: 1
+
+ arm-supply:
+ deprecated: true
+ description: Use 'cpu-supply' instead
+
+ cpu0-supply:
+ deprecated: true
+ description: Use 'cpu-supply' instead
+
+ mem-supply: true
+
+ proc-supply:
+ deprecated: true
+ description: Use 'cpu-supply' instead
+
+ sram-supply:
+ deprecated: true
+ description: Use 'mem-supply' instead
+
+ mediatek,cci:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Link to Mediatek Cache Coherent Interconnect
+
qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -327,6 +362,11 @@ properties:
description:
Specifies the ACC node associated with this CPU.
+ qcom,freq-domain:
+ description: Specifies the QCom CPUFREQ HW associated with the CPU.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description: >
@@ -352,7 +392,11 @@ properties:
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
+ thermal-idle:
+ type: object
+
allOf:
+ - $ref: /schemas/cpu.yaml#
- $ref: /schemas/opp/opp-v1.yaml#
- if:
# If the enable-method property contains one of those values
@@ -416,7 +460,7 @@ required:
dependencies:
rockchip,pmu: [enable-method]
-additionalProperties: true
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml
index 1b59b103dab6..61c080e50859 100644
--- a/Documentation/devicetree/bindings/opp/opp-v1.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml
@@ -21,6 +21,18 @@ description: |+
deprecated: true
properties:
+ clock-latency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The latency in nanoseconds for clock changes. Use OPP tables for new
+ designs instead.
+
+ voltage-tolerance:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 10
+ description:
+ The voltage tolerance in percent. Use OPP tables for new designs instead.
+
operating-points:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
@@ -28,8 +40,12 @@ properties:
- description: Frequency in kHz
- description: Voltage for OPP in uV
+dependencies:
+ clock-latency: [ operating-points ]
+ voltage-tolerance: [ operating-points ]
additionalProperties: true
+
examples:
- |
cpus {
--
2.47.2
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