linux-kernel - Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock

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Message-ID: <20250410204845.GA1027003-robh@kernel.org>
Date: Thu, 10 Apr 2025 15:48:45 -0500
From: Rob Herring <robh@...nel.org>
To: Marek Vasut <marek.vasut+renesas@...lbox.org>
Cc: linux-arm-kernel@...ts.infradead.org,
	Niklas Söderlund <niklas.soderlund+renesas@...natech.se>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Rafał Miłecki <rafal@...ecki.pl>,
	Aradhya Bhatia <a-bhatia1@...com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Heiko Stuebner <heiko@...ech.de>, Junhao Xie <bigfoot@...ssfun.cn>,
	Kever Yang <kever.yang@...k-chips.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document
 optional aux clock

On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> Document 'aux' clock which are used to supply the PCIe bus. This
> is useful in case of a hardware setup, where the PCIe controller
> input clock and the PCIe bus clock are supplied from the same
> clock synthesiser, but from different differential clock outputs:
> 
>  ____________                    _____________
> | R-Car PCIe |                  | PCIe device |
> |            |                  |             |
> |    PCIe RX<|==================|>PCIe TX     |
> |    PCIe TX<|==================|>PCIe RX     |
> |            |                  |             |
> |   PCIe CLK<|======..  ..======|>PCIe CLK    |
> '------------'      ||  ||      '-------------'
>                     ||  ||
>  ____________       ||  ||
> |  9FGV0441  |      ||  ||
> |            |      ||  ||
> |   CLK DIF0<|======''  ||
> |   CLK DIF1<|==========''
> |   CLK DIF2<|
> |   CLK DIF3<|
> '------------'
> 
> The clock are named 'aux' because those are one of the clock listed in
> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which
> fit closest to the PCIe bus clock. According to that binding document,
> the 'aux' clock describe clock which supply the PMC domain, which is
> likely PCIe Mezzanine Card domain.

Pretty sure that PMC is "power management controller" given it talks 
about low power states.


> 
> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@...natech.se>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@...lbox.org>
> ---
> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
>       instead and add 'bus' clock outright ?

Based on the diagram, this has nothing to do with the specific 
controller. It should also probably a root port property, not host 
bridge.

Rob