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Message-ID: <Z_g8Py8Ow85Uj6RT@google.com>
Date: Thu, 10 Apr 2025 14:46:39 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Borislav Petkov <bp@...nel.org>
Cc: Paolo Bonzini <pbonzini@...hat.com>, X86 ML <x86@...nel.org>, KVM <kvm@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>, "Borislav Petkov (AMD)" <bp@...en8.de>
Subject: Re: [PATCH] KVM: x86: Sort CPUID_8000_0021_EAX leaf bits properly
On Mon, Mar 24, 2025, Borislav Petkov wrote:
> From: "Borislav Petkov (AMD)" <bp@...en8.de>
>
> WRMSR_XX_BASE_NS is bit 1 so put it there, add some new bits as
> comments only.
>
> Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
> ---
> arch/x86/kvm/cpuid.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 121edf1f2a79..e98ab18f784b 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -1160,6 +1160,7 @@ void kvm_set_cpu_caps(void)
>
> kvm_cpu_cap_init(CPUID_8000_0021_EAX,
> F(NO_NESTED_DATA_BP),
> + F(WRMSR_XX_BASE_NS),
> /*
> * Synthesize "LFENCE is serializing" into the AMD-defined entry
> * in KVM's supported CPUID, i.e. if the feature is reported as
> @@ -1173,10 +1174,14 @@ void kvm_set_cpu_caps(void)
> SYNTHESIZED_F(LFENCE_RDTSC),
> /* SmmPgCfgLock */
> F(NULL_SEL_CLR_BASE),
> + /* UpperAddressIgnore */
> F(AUTOIBRS),
> EMULATED_F(NO_SMM_CTL_MSR),
> + /* FSRS */
> + /* FSRC */
I'm going to skip these, as they aren't yet publicly documented, and there are
patches proposed to add actual support. I wouldn't care all that much if these
didn't collide with Intel's version (the proposed patches name them AMD_FSxx).
https://lore.kernel.org/all/20241204134345.189041-2-davydov-max@yandex-team.ru
> /* PrefetchCtlMsr */
> - F(WRMSR_XX_BASE_NS),
> + /* GpOnUserCpuid */
> + /* EPSF */
FWIW, this one's also not in the APM (though the only APM I can find is a year old),
though it's in tools/x86/kcpuid.
> SYNTHESIZED_F(SBPB),
> SYNTHESIZED_F(IBPB_BRTYPE),
> SYNTHESIZED_F(SRSO_NO),
> --
> 2.43.0
>
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