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Message-ID: <4ef3b2464691d65a295d0f5669e27f8a5382ea06.camel@gmail.com>
Date: Thu, 10 Apr 2025 10:40:16 +0100
From: Nuno Sá <noname.nuno@...il.com>
To: Marcelo Schmitt <marcelo.schmitt@...log.com>, linux-iio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: jic23@...nel.org, lars@...afoo.de, Michael.Hennerich@...log.com,
dlechner@...libre.com, nuno.sa@...log.com, andy@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
marcelo.schmitt1@...il.com
Subject: Re: [PATCH v1 4/7] iio: adc: ad4170: Add clock provider support
On Wed, 2025-04-09 at 09:25 -0300, Marcelo Schmitt wrote:
> The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or
> an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively,
> the AD4170 can provide it's 16 MHz internal clock at the XTAL2 pin. Extend
> the AD4170 driver so it effectively uses the provided external clock, if
> any, or supplies it's own clock as a clock provider.
>
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@...log.com>
> ---
Just one minor note, with it:
Reviewed-by: Nuno Sá <nuno.sa@...log.com>
> drivers/iio/adc/ad4170.c | 135 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 134 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c
> index 5ffcdedf3e7f..97cf4465038f 100644
> --- a/drivers/iio/adc/ad4170.c
> +++ b/drivers/iio/adc/ad4170.c
> @@ -7,6 +7,8 @@
>
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/err.h>
> @@ -62,6 +64,7 @@
> #define AD4170_DATA_16B_STATUS_REG 0x1A
> #define AD4170_DATA_24B_REG 0x1E
> #define AD4170_PIN_MUXING_REG 0x69
> +#define AD4170_CLOCK_CTRL_REG 0x6B
> #define AD4170_ADC_CTRL_REG 0x71
> #define AD4170_CHAN_EN_REG 0x79
> #define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x))
> @@ -89,6 +92,9 @@
> #define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)
> #define AD4170_PIN_MUXING_SYNC_CTRL_MSK GENMASK(3, 2)
>
> +/* AD4170_CLOCK_CTRL_REG */
> +#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0)
> +
> /* AD4170_ADC_CTRL_REG */
> #define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
> #define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
> @@ -121,6 +127,12 @@
>
> /* AD4170 register constants */
>
> +/* AD4170_CLOCK_CTRL_REG constants */
> +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0
> +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1
> +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2
> +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3
> +
> /* AD4170_CHAN_MAP_REG constants */
> #define AD4170_CHAN_MAP_AIN0 0
> #define AD4170_CHAN_MAP_AIN1 1
> @@ -238,6 +250,10 @@ enum ad4170_regulator {
> AD4170_MAX_SUP
> };
>
> +static const char *const ad4170_clk_sel[] = {
> + "ext-clk", "xtal"
> +};
> +
> enum ad4170_int_pin_sel {
> AD4170_INT_PIN_SDO,
> AD4170_INT_PIN_DIG_AUX1,
> @@ -320,6 +336,9 @@ struct ad4170_state {
> struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS];
> struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
> u32 mclk_hz;
> + unsigned int clock_ctrl;
> + struct clk *ext_clk;
> + struct clk_hw int_clk_hw;
> int pins_fn[AD4170_NUM_ANALOG_PINS];
> u32 int_pin_sel;
> int
> sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
> @@ -1693,13 +1712,127 @@ static int ad4170_parse_channels(struct iio_dev
> *indio_dev)
> return 0;
> }
>
> +static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw)
> +{
> + return container_of(hw, struct ad4170_state, int_clk_hw);
> +}
> +
> +static unsigned long ad4170_sel_clk(struct ad4170_state *st,
> + unsigned int clk_sel)
> +{
> + st->clock_ctrl &= ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK;
> + st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
> clk_sel);
> + return regmap_write(st->regmap16, AD4170_CLOCK_CTRL_REG, st-
> >clock_ctrl);
> +}
> +
> +static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + return AD4170_INT_CLOCK_16MHZ;
> +}
> +
> +static int ad4170_clk_output_is_enabled(struct clk_hw *hw)
> +{
> + struct ad4170_state *st = clk_hw_to_ad4170(hw);
> + u32 clk_sel;
> +
> + clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl);
> + return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT;
> +}
> +
> +static int ad4170_clk_output_prepare(struct clk_hw *hw)
> +{
> + struct ad4170_state *st = clk_hw_to_ad4170(hw);
> +
> + return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT);
> +}
> +
> +static void ad4170_clk_output_unprepare(struct clk_hw *hw)
> +{
> + struct ad4170_state *st = clk_hw_to_ad4170(hw);
> +
> + ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT);
> +}
> +
> +static const struct clk_ops ad4170_int_clk_ops = {
> + .recalc_rate = ad4170_clk_recalc_rate,
> + .is_enabled = ad4170_clk_output_is_enabled,
> + .prepare = ad4170_clk_output_prepare,
> + .unprepare = ad4170_clk_output_unprepare,
> +};
> +
> +static int ad4170_register_clk_provider(struct iio_dev *indio_dev)
> +{
> + struct ad4170_state *st = iio_priv(indio_dev);
> + struct device *dev = indio_dev->dev.parent;
> + struct fwnode_handle *fwnode = dev_fwnode(dev);
> + struct clk_init_data init = {};
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_COMMON_CLK))
> + return 0;
> +
> + init.name = fwnode_get_name(fwnode);
Maybe allow for clock-output-names? See:
https://elixir.bootlin.com/linux/v6.13.7/source/drivers/iio/frequency/adf4350.c#L467
- Nuno Sá
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