linux-kernel - Re: [PATCH v3 1/3] arm64: dts: rockchip: add mipi dcphy nodes to rk3588

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Message-ID: <lvn74g6bcw2bxd3ciizso6pfvhp3ulxhmqrxm67zjcdx674fnv@3sxsqwsv5bin>
Date: Fri, 11 Apr 2025 14:33:56 +0200
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Heiko Stuebner <heiko@...ech.de>
Cc: quentin.schulz@...rry.de, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	dse@...umatec.com, Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: Re: [PATCH v3 1/3] arm64: dts: rockchip: add mipi dcphy nodes to
 rk3588

Hi,

On Wed, Feb 26, 2025 at 03:09:40PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@...rry.de>
> 
> Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the
> DSI2 controllers and hopefully in some future also for camera input.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@...labora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@...labora.com> # RK3588 EVB1

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 8b497eb5da16..5535d5d905f6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -574,6 +574,16 @@ sys_grf: syscon@...8c000 {
>  		reg = <0x0 0xfd58c000 0x0 0x1000>;
>  	};
>  
> +	mipidcphy0_grf: syscon@...e8000 {
> +		compatible = "rockchip,rk3588-dcphy-grf", "syscon";
> +		reg = <0x0 0xfd5e8000 0x0 0x4000>;
> +	};
> +
> +	mipidcphy1_grf: syscon@...ec000 {
> +		compatible = "rockchip,rk3588-dcphy-grf", "syscon";
> +		reg = <0x0 0xfd5ec000 0x0 0x4000>;
> +	};
> +
>  	vop_grf: syscon@...a4000 {
>  		compatible = "rockchip,rk3588-vop-grf", "syscon";
>  		reg = <0x0 0xfd5a4000 0x0 0x2000>;
> @@ -2915,6 +2925,38 @@ usbdp_phy0: phy@...80000 {
>  		status = "disabled";
>  	};
>  
> +	mipidcphy0: phy@...a0000 {
> +		compatible = "rockchip,rk3588-mipi-dcphy";
> +		reg = <0x0 0xfeda0000 0x0 0x10000>;
> +		rockchip,grf = <&mipidcphy0_grf>;
> +		clocks = <&cru PCLK_MIPI_DCPHY0>,
> +			 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> +		clock-names = "pclk", "ref";
> +		resets = <&cru SRST_M_MIPI_DCPHY0>,
> +			 <&cru SRST_P_MIPI_DCPHY0>,
> +			 <&cru SRST_P_MIPI_DCPHY0_GRF>,
> +			 <&cru SRST_S_MIPI_DCPHY0>;
> +		reset-names = "m_phy", "apb", "grf", "s_phy";
> +		#phy-cells = <1>;
> +		status = "disabled";
> +	};
> +
> +	mipidcphy1: phy@...b0000 {
> +		compatible = "rockchip,rk3588-mipi-dcphy";
> +		reg = <0x0 0xfedb0000 0x0 0x10000>;
> +		rockchip,grf = <&mipidcphy1_grf>;
> +		clocks = <&cru PCLK_MIPI_DCPHY1>,
> +			 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> +		clock-names = "pclk", "ref";
> +		resets = <&cru SRST_M_MIPI_DCPHY1>,
> +			 <&cru SRST_P_MIPI_DCPHY1>,
> +			 <&cru SRST_P_MIPI_DCPHY1_GRF>,
> +			 <&cru SRST_S_MIPI_DCPHY1>;
> +		reset-names = "m_phy", "apb", "grf", "s_phy";
> +		#phy-cells = <1>;
> +		status = "disabled";
> +	};
> +
>  	combphy0_ps: phy@...00000 {
>  		compatible = "rockchip,rk3588-naneng-combphy";
>  		reg = <0x0 0xfee00000 0x0 0x100>;
> -- 
> 2.47.2
> 
> 

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