linux-kernel - Re: [PATCH v3 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility

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Message-ID: <20250411-backward-mountain-3dd2b913f9f9@spud>
Date: Fri, 11 Apr 2025 17:25:47 +0100
From: Conor Dooley <conor@...nel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Min Lin <linmin@...incomputing.com>,
	Pritesh Patel <pritesh.patel@...fochips.com>,
	Yangyu Chen <cyy@...self.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Yu Chien Peter Lin <peterlin@...estech.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Kanak Shilledar <kanakshilledar@...il.com>,
	Darshan Prajapati <darshan.prajapati@...fochips.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Heiko Stuebner <heiko@...ech.de>, Aradhya Bhatia <a-bhatia1@...com>,
	rafal@...ecki.pl, Anup Patel <anup@...infault.org>,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN
 EIC7700 SoC compatibility

On Thu, Apr 10, 2025 at 08:55:14PM +0530, Pinkesh Vaghela wrote:
> From: Pritesh Patel <pritesh.patel@...fochips.com>
> 
> This cache controller is also used on the ESWIN EIC7700 SoC.
> However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
> So add dedicated compatible string for it.
> 
> Signed-off-by: Pritesh Patel <pritesh.patel@...fochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>

This and the cache driver patch have already been applied.

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