linux-kernel - RE: [PATCH 0/7] Enhance the PCIe controller driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <CH2PPF4D26F8E1C08E292813424DCF669BCA2B62@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>
Date: Fri, 11 Apr 2025 04:08:54 +0000
From: Manikandan Karunakaran Pillai <mpillai@...ence.com>
To: "manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "lpieralisi@...nel.org"
	<lpieralisi@...nel.org>,
        "kw@...ux.com" <kw@...ux.com>, "robh@...nel.org"
	<robh@...nel.org>,
        "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        Milind Parab
	<mparab@...ence.com>,
        "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/7] Enhance the PCIe controller driver

>
>EXTERNAL MAIL
>
>
>On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai
>wrote:
>> Enhances the exiting Cadence PCIe controller drivers to support second
>> generation PCIe controller also referred as HPA(High Performance
>> Architecture) controllers.
>>
>> The patch set enhances the Cadence PCIe driver for the new high
>> performance architecture changes. The "compatible" property in DTS
>> is added with  more strings to support the new platform architecture
>> and the register maps that change with it. The driver read register
>> and write register functions take the updated offset stored from the
>> platform driver to access the registers. The driver now supports
>> the legacy and HPA architecture, with the legacy code being changed
>> minimal. The TI SoC continues to be supported with the changes
>> incorporated. The changes are also in tune with how multiple platforms
>> are supported in related drivers.
>>
>> Patch 1/7 - DTS related changes for property "compatible"
>> Patch 2/7 - Updates the header file with relevant register offsets and
>>             bit definitions
>> Patch 3/7 - Platform related code changes
>> Patch 4/7 - PCIe EP related code changes
>> Patch 5/7 - Header file is updated with register offsets and updated
>>             read and write register functions
>> Patch 6/7 - Support for multiple arch by using registered callbacks
>> Patch 7/7 - TIJ72X board is updated to use the new approach
>
>This one line patch summary is not useful. We can look into individual patches.
>

Will remove this one in the next submission

>>
>
>This series is v2. Please use version in the subject prefix and also include the
>changelog section.
>
Plan to send out the next patch as v3.

>> Comments from the earlier patch submission on the same enhancements
>are
>> taken into consideration. The previous submitted patch links is
>>
>https://urldefense.com/v3/__https://lore.kernel.org/lkml/CH2PPF4D26F8E1C20
>5166209F012D4F3A81A2A42@...PPF4D26F8E1C.namprd07.prod.outlook.co
>m/__;!!EHscmS1ygiU1lA!HHaKm1CBv1jpRLP6XLRHiZaHXTVDW7dtEXp1k5GrzL6
>sEZ5avF7nkcTmTRc-xU1glrJLmydxfi_HvLkwChItFEwo2Do$
>>
>
>This is not how you would add changelog in cover letter. Please read:
>Documentation/process/submitting-patches.rst

OK

>
>- Mani
>
>--
>மணிவண்ணன் சதாசிவம்