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Message-ID: <e3dda8bf-e19e-4dde-83a4-7876ca81e5e6@oss.qualcomm.com>
Date: Fri, 11 Apr 2025 11:12:44 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Jagadeesh Kona <quic_jkona@...cinc.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Luca Weiss <luca.weiss@...rphone.com>,
Bjorn Andersson
<andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Taniya Das <quic_tdas@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: sm6350: Add video clock
controller
On 4/11/25 9:15 AM, Jagadeesh Kona wrote:
>
>
> On 4/1/2025 10:03 PM, Konrad Dybcio wrote:
>> On 3/24/25 9:41 AM, Luca Weiss wrote:
>>> Add a node for the videocc found on the SM6350 SoC.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 14 ++++++++++++++
>>> 1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> index 42f9d16c2fa6da66a8bb524a33c2687a1e4b40e0..4498d6dfd61a7e30a050a8654d54dae2d06c220c 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> @@ -1952,6 +1952,20 @@ usb_1_dwc3_ss_out: endpoint {
>>> };
>>> };
>>>
>>> + videocc: clock-controller@...0000 {
>>> + compatible = "qcom,sm6350-videocc";
>>> + reg = <0x0 0x0aaf0000 0x0 0x10000>;
>>> + clocks = <&gcc GCC_VIDEO_AHB_CLK>,
>>> + <&rpmhcc RPMH_CXO_CLK>,
>>> + <&sleep_clk>;
>>> + clock-names = "iface",
>>> + "bi_tcxo",
>>> + "sleep_clk";
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> + #power-domain-cells = <1>;
>>> + };
>>
>> You'll probably want to hook up some additional power domains here, see
>>
>> https://lore.kernel.org/linux-arm-msm/20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com/
>>
>
> On SM6350, videocc doesn't need multiple power domains at HW level, it is only on CX rail which would be ON
> when system is active, hence power-domains are not mandatory here.
6350 doesn't have either MMCX nor a split MX - shouldn't both normal
CX and MX be in there?
Konrad
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