linux-kernel - Re: [PATCH v3 1/2] x86: KVM: Advertise FSRS and FSRC on AMD to userspace

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Message-ID: <20250411094059.GIZ_jjq0DxLhJOEQ9B@fat_crate.local>
Date: Fri, 11 Apr 2025 11:40:59 +0200
From: Borislav Petkov <bp@...en8.de>
To: Maksim Davydov <davydov-max@...dex-team.ru>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org, x86@...nel.org,
	babu.moger@....com, seanjc@...gle.com, mingo@...hat.com,
	tglx@...utronix.de, dave.hansen@...ux.intel.com, hpa@...or.com,
	jmattson@...gle.com, pbonzini@...hat.com
Subject: Re: [PATCH v3 1/2] x86: KVM: Advertise FSRS and FSRC on AMD to
 userspace

On Wed, Dec 04, 2024 at 04:43:44PM +0300, Maksim Davydov wrote:
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 17b6590748c0..45f87a026bba 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -460,6 +460,8 @@
>  #define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */
>  #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
>  #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
> +#define X86_FEATURE_AMD_FSRS	        (20*32+10) /* AMD Fast short REP STOSB supported */
> +#define X86_FEATURE_AMD_FSRC		(20*32+11) /* AMD Fast short REP CMPSB supported */

Since Intel has the same flags, you should do

	if (cpu_has(c, X86_FEATURE_AMD_FSRS))
		set_cpu_cap(c, X86_FEATURE_FSRS);

and the other one too. Probably in init_amd() so that guest userspace doesn't
need to differentiate between the two and you don't have to do...

>  #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
>  #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 097bdc022d0f..7bc095add8ee 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -799,8 +799,8 @@ void kvm_set_cpu_caps(void)
>  
>  	kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
>  		F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
> -		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
> -		F(WRMSR_XX_BASE_NS)
> +		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | F(AMD_FSRS) |
> +		F(AMD_FSRC) | 0 /* PrefetchCtlMsr */ | F(WRMSR_XX_BASE_NS)

... this.

-- 
Regards/Gruss,
    Boris.

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