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Message-ID: <20250411105155.303657-4-j-choudhary@ti.com>
Date: Fri, 11 Apr 2025 16:21:51 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <nm@...com>, <vigneshr@...com>, <u-kumar1@...com>, <devarsht@...com>,
<linux-kernel@...r.kernel.org>
CC: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<kristo@...nel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <j-choudhary@...com>
Subject: [PATCH 3/7] arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY
From: Rahul T R <r-ravikumar@...com>
Add DT nodes for DPI to DSI Bridge and DSI Phy.
The DSI bridge is Cadence DSI and the PHY is a
Cadence DPHY with TI wrapper.
Signed-off-by: Rahul T R <r-ravikumar@...com>
[j-choudhary@...com: disable dsi and dphy nodes, rename dphy node]
Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 92bf48fdbeba..b91943349024 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1790,6 +1790,43 @@ main_spi7: spi@...0000 {
status = "disabled";
};
+ dphy_tx0: phy@...0000 {
+ compatible = "ti,j721e-dphy";
+ reg = <0x0 0x04480000 0x0 0x1000>;
+ clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 363 14>;
+ assigned-clock-parents = <&k3_clks 363 15>;
+ assigned-clock-rates = <19200000>;
+ status = "disabled";
+ };
+
+ dsi0: dsi@...0000 {
+ compatible = "ti,j721e-dsi";
+ reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
+ clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ dsi0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
dss: dss@...0000 {
compatible = "ti,j721e-dss";
reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
--
2.34.1
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