linux-kernel - Re: [PATCH v3 4/4] x86/CPU/AMD: Print the reason for the last reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250411120617.GMZ_kFucLFQQ7LJkys@fat_crate.local>
Date: Fri, 11 Apr 2025 14:06:17 +0200
From: Borislav Petkov <bp@...en8.de>
To: Mario Limonciello <superm1@...nel.org>
Cc: Jean Delvare <jdelvare@...e.com>, Andi Shyti <andi.shyti@...nel.org>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	Jonathan Corbet <corbet@....net>,
	Mario Limonciello <mario.limonciello@....com>,
	Yazen Ghannam <yazen.ghannam@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
	"H . Peter Anvin" <hpa@...or.com>,
	Shyam Sundar S K <Shyam-sundar.S-k@....com>,
	Hans de Goede <hdegoede@...hat.com>,
	"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
	open list <linux-kernel@...r.kernel.org>,
	"open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC" <linux-i2c@...r.kernel.org>,
	"open list:AMD PMC DRIVER" <platform-driver-x86@...r.kernel.org>
Subject: Re: [PATCH v3 4/4] x86/CPU/AMD: Print the reason for the last reset

On Thu, Apr 10, 2025 at 03:02:02PM -0500, Mario Limonciello wrote:
> +static __init int print_s5_reset_status_mmio(void)
> +{
> +	void __iomem *addr;
> +	unsigned long value;
> +	int bit = -1;
> +
> +	if (!cpu_feature_enabled(X86_FEATURE_ZEN))
> +		return 0;
> +
> +	addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
> +	if (!addr)
> +		return 0;

newline.

> +	value = ioread32(addr);
> +	iounmap(addr);
> +
> +	do {
> +		bit = find_next_bit(&value, BITS_PER_LONG, bit + 1);
> +	} while (!s5_reset_reason_txt[bit]);

What's the idea here? The highest bit is the most fitting one?

So why don't you do fls() or so?

> +	pr_info("x86/amd: Previous system reset reason [0x%08lx]: %s\n",
> +		value, s5_reset_reason_txt[bit]);

What's guaranteeing that s5_reset_reason_txt[bit] is still set here?

I'd suggest you check it again and never trust the hw because we'll be fixing
a null ptr here at some point otherwise...

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette