linux-kernel - Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready

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Message-ID: <h7pja24zffl4t7653rjaamp6v2j5nmukbzq7rdajynemlyb6l6@3e37ggkparjg>
Date: Sun, 13 Apr 2025 21:08:45 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Hongxing Zhu <hongxing.zhu@....com>
Cc: Frank Li <frank.li@....com>, 
	"l.stach@...gutronix.de" <l.stach@...gutronix.de>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>, 
	"kw@...ux.com" <kw@...ux.com>, "robh@...nel.org" <robh@...nel.org>, 
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "shawnguo@...nel.org" <shawnguo@...nel.org>, 
	"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>, "kernel@...gutronix.de" <kernel@...gutronix.de>, 
	"festevam@...il.com" <festevam@...il.com>, "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, 
	"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit
 L23 ready

On Thu, Apr 10, 2025 at 02:45:51AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > Sent: 2025年4月10日 0:44
> > To: Hongxing Zhu <hongxing.zhu@....com>
> > Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de; lpieralisi@...nel.org;
> > kw@...ux.com; robh@...nel.org; bhelgaas@...gle.com;
> > shawnguo@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> > festevam@...il.com; linux-pci@...r.kernel.org;
> > linux-arm-kernel@...ts.infradead.org; imx@...ts.linux.dev;
> > linux-kernel@...r.kernel.org
> > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> > ready
> > 
> > On Tue, Apr 08, 2025 at 03:02:42AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Hongxing Zhu
> > > > Sent: 2025年4月3日 11:23
> > > > To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > > > Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> > > > lpieralisi@...nel.org; kw@...ux.com; robh@...nel.org;
> > > > bhelgaas@...gle.com; shawnguo@...nel.org; s.hauer@...gutronix.de;
> > > > kernel@...gutronix.de; festevam@...il.com;
> > > > linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> > > > imx@...ts.linux.dev; linux-kernel@...r.kernel.org
> > > > Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > not exit
> > > > L23 ready
> > > >
> > > > > -----Original Message-----
> > > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > > > > Sent: 2025年4月2日 23:18
> > > > > To: Hongxing Zhu <hongxing.zhu@....com>
> > > > > Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> > > > > lpieralisi@...nel.org; kw@...ux.com; robh@...nel.org;
> > > > > bhelgaas@...gle.com; shawnguo@...nel.org; s.hauer@...gutronix.de;
> > > > > kernel@...gutronix.de; festevam@...il.com;
> > > > > linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> > > > > imx@...ts.linux.dev; linux-kernel@...r.kernel.org
> > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > > not exit L23 ready
> > > > >
> > > > > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > > > > -----Original Message-----
> > > > > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > > > > > > Sent: 2025年4月2日 15:08
> > > > > > > To: Hongxing Zhu <hongxing.zhu@....com>
> > > > > > > Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> > > > > > > lpieralisi@...nel.org; kw@...ux.com; robh@...nel.org;
> > > > > > > bhelgaas@...gle.com; shawnguo@...nel.org;
> > > > > > > s.hauer@...gutronix.de; kernel@...gutronix.de;
> > > > > > > festevam@...il.com; linux-pci@...r.kernel.org;
> > > > > > > linux-arm-kernel@...ts.infradead.org;
> > > > > > > imx@...ts.linux.dev; linux-kernel@...r.kernel.org
> > > > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe
> > > > > > > may not exit L23 ready
> > > > > > >
> > > > > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > > > > > Through Beacon or PERST# De-assertion
> > > > > > >
> > > > > > > Is it possible to share the link to the erratum?
> > > > > > >
> > > > > > Sorry, the erratum document isn't ready to be published yet.
> > > > > > > >
> > > > > > > > When the auxiliary power is not available, the controller
> > > > > > > > cannot exit from
> > > > > > > > L23 Ready with beacon or PERST# de-assertion when main power
> > > > > > > > is not removed.
> > > > > > > >
> > > > > > >
> > > > > > > I don't understand how the presence of Vaux affects the controller.
> > > > > > > Same goes for PERST# deassertion. How does that relate to
> > > > > > > Vaux? Is this erratum for a specific endpoint behavior?
> > > > > > IMHO I don't know the exact details of the power supplies in this IP
> > design.
> > > > > > Refer to my guess , maybe the beacon detect or wake-up logic in
> > > > > > designs is  relied on the status of SYS_AUX_PWR_DET signals in this
> > case.
> > > > >
> > > > > Can you please try to get more details? I couldn't understand the errata.
> > > > >
> > > > Sure. Will contact designer and try to get more details.
> > > Hi Mani:
> > > Get some information from designs, the internal design logic is relied
> > > on the  status of SYS_AUX_PWR_DET signal to handle the low power stuff.
> > > So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW workaround.
> > >
> > 
> > Ok. So due to the errata, when the link enters L23 Ready state, it cannot
> > transition to L3 when Vaux is not available. And the workaround requires setting
> > SYS_AUX_PWR_DET bit?
> > 
> Refer to the description of this errata, it just mentions the exist from
>  L23 Ready state.

Exiting from L23 Ready == entering L2/L3. And since you mentioned that Vaux is
not available, it is definitely entering L3.

> Yes, the workaround requires setting SYS_AUX_PWR_DET bit to 1b'1.
> 
> > IIUC, the issue here is that the controller is not able to detect the presence of
> > Vaux in the L23 Ready state. So it relies on the SYS_AUX_PWR_DET bit. But even
> > in that case, how would you support the endpoint *with* Vaux?
> > 
> This errata is only applied for i.MX95 dual PCIe mode controller.
> The Vaux is not present for i.MX95 PCIe EP mode either.
> 

First of all, does the controller really know whether Vaux is supplied to the
endpoint or not? AFAIK, it is up to the board designers to route Vaux and only
endpoint should care about it.

I still feel that this specific erratum is for fixing the issue with some
endpoints where Vaux is not supplied and the link doesn't exit L23 Ready. Again,
what would be the behavior if Vaux is supplied to the endpoint? You cannot just
say that the controller doesn't support Vaux, which is not a valid statement
IMO.

- Mani

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