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Message-ID: <20250414214330-GYA29591@gentoo>
Date: Mon, 14 Apr 2025 21:43:30 +0000
From: Yixun Lan <dlan@...too.org>
To: Alex Elder <elder@...cstar.com>
Cc: Haylen Chu <heylenay@....org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Haylen Chu <heylenay@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
spacemit@...ts.linux.dev, Inochi Amaoto <inochiama@...look.com>,
Chen Wang <unicornxdotw@...mail.com>,
Jisheng Zhang <jszhang@...nel.org>,
Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>
Subject: Re: [PATCH v7 3/6] clk: spacemit: Add clock support for SpacemiT K1
SoC
On 13:12 Mon 14 Apr , Alex Elder wrote:
> On 4/12/25 2:44 AM, Haylen Chu wrote:
> > The clock tree of K1 SoC contains three main types of clock hardware
> > (PLL/DDN/MIX) and has control registers split into several multifunction
> > devices: APBS (PLLs), MPMU, APBC and APMU.
> >
> > All register operations are done through regmap to ensure atomiciy
>
> s/atomiciy/atomicity/
>
> I think Yixun can tweak that for you.
>
sure, I will take care of it..
(if there is no more iteration)
> > between concurrent operations of clock driver and reset,
> > power-domain driver that will be introduced in the future.
> >
> > Signed-off-by: Haylen Chu <heylenay@....org>
>
> This looks good to me!
>
> Reviewed-by: Alex Elder <elder@...cstar.com>
>
thanks
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
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