linux-kernel - Re: [RFC 5/5] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2

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Message-ID: <e243cca4-40d7-4cd6-804a-7e63bb5581b0@collabora.com>
Date: Mon, 14 Apr 2025 12:27:30 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Frank Wunderlich <linux@...web.de>,
 Chunfeng Yun <chunfeng.yun@...iatek.com>, Vinod Koul <vkoul@...nel.org>,
 Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
 Daniel Golle <daniel@...rotopia.org>, Sam Shih <sam.shih@...iatek.com>,
 MandyJH Liu <mandyjh.liu@...iatek.com>,
 linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
 linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [RFC 5/5] arm64: dts: mediatek: mt7988: Add xsphy for
 ssusb0/pcie2

Il 13/04/25 10:58, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w@...lic-files.de>
> 
> First usb and third pcie controller on mt7988 need a xs-phy to work
> properly.
> 
> Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
> ---
>   arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++
>   1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index 88b56a24efca..10525d977007 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -334,6 +334,8 @@ usb@...90000 {
>   				 <&infracfg CLK_INFRA_133M_USB_HCK>,
>   				 <&infracfg CLK_INFRA_USB_XHCI>;
>   			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
> +			phys = <&xphyu2port0 PHY_TYPE_USB2>,
> +			       <&xphyu3port0 PHY_TYPE_USB3>;
>   			status = "disabled";
>   		};
>   
> @@ -398,6 +400,9 @@ pcie2: pcie@...80000 {
>   			pinctrl-0 = <&pcie2_pins>;
>   			status = "disabled";
>   
> +			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
> +			phy-names = "pcie-phy";
> +
>   			#interrupt-cells = <1>;
>   			interrupt-map-mask = <0 0 0 0x7>;
>   			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
> @@ -548,6 +553,40 @@ tphyu3port0: usb-phy@...50700 {
>   			};
>   		};
>   
> +		topmisc: power-controller@...10000 {
> +			compatible = "mediatek,mt7988-topmisc", "syscon",
> +				     "mediatek,mt7988-power-controller";
> +			reg = <0 0x11d10000 0 0x10000>;
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		xs-phy@...10000 {

That shall be just "phy@...r"

> +			compatible = "mediatek,mt7988-xsphy",
> +				     "mediatek,xsphy";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			xphyu2port0: usb-phy@...10000 {

Perhaps just u2port0/u3port0 like done on the other MediaTek SoC DTs is better
for consistency :-)

Cheers!

> +				reg = <0 0x11e10000 0 0x400>;
> +				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			xphyu3port0: usb-phy@...13000 {
> +				reg = <0 0x11e13400 0 0x500>;
> +				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +				mediatek,syscon-type = <&topmisc 0x218 0>;
> +			};
> +		};
> +
>   		clock-controller@...40000 {
>   			compatible = "mediatek,mt7988-xfi-pll";
>   			reg = <0 0x11f40000 0 0x1000>;