linux-kernel - RE: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

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Message-ID:
 <AS8PR04MB8676883E80A61FF28FBB4C188CB32@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Mon, 14 Apr 2025 03:18:56 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
CC: Frank Li <frank.li@....com>, "l.stach@...gutronix.de"
	<l.stach@...gutronix.de>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kw@...ux.com" <kw@...ux.com>, "robh@...nel.org" <robh@...nel.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "shawnguo@...nel.org"
	<shawnguo@...nel.org>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
	"kernel@...gutronix.de" <kernel@...gutronix.de>, "festevam@...il.com"
	<festevam@...il.com>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Sent: 2025年4月13日 23:18
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> lpieralisi@...nel.org; kw@...ux.com; robh@...nel.org;
> bhelgaas@...gle.com; shawnguo@...nel.org; s.hauer@...gutronix.de;
> kernel@...gutronix.de; festevam@...il.com; linux-pci@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; imx@...ts.linux.dev;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe
> 
> On Tue, Apr 08, 2025 at 10:59:26AM +0800, Richard Zhu wrote:
> > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
> 
> Please avoid spelling mistakes in the commit messages.
> 
Okay, would be replaced by the following one.
Add a cold reset toggle for the i.MX95 PCIe to align the PHY's power-up
 sequence.

> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> 
> Reviewed-by: Manivannan Sadhasivam
> <manivannan.sadhasivam@...aro.org>
> 
Thanks.
Best Regards
Richard

> - Mani
> 
> > Reviewed-by: Frank Li <Frank.Li@....com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 42
> > +++++++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index c5871c3d4194..7c60b712480a 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -71,6 +71,9 @@
> >  #define IMX95_SID_MASK				GENMASK(5, 0)
> >  #define IMX95_MAX_LUT				32
> >
> > +#define IMX95_PCIE_RST_CTRL			0x3010
> > +#define IMX95_PCIE_COLD_RST			BIT(0)
> > +
> >  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
> >
> >  enum imx_pcie_variants {
> > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie
> *imx_pcie, bool assert)
> >  	return 0;
> >  }
> >
> > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool
> > +assert) {
> > +	u32 val;
> > +
> > +	if (assert) {
> > +		/*
> > +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> > +		 * should be complete after power-up by the following sequence.
> > +		 *                 > 10us(at power-up)
> > +		 *                 > 10ns(warm reset)
> > +		 *               |<------------>|
> > +		 *                ______________
> > +		 * phy_reset ____/              \________________
> > +		 *                                   ____________
> > +		 * ref_clk_en_______________________/
> > +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> > +		 */
> > +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				IMX95_PCIE_COLD_RST);
> > +		/*
> > +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> > +		 * hardware by doing a read. Otherwise, there is no guarantee
> > +		 * that the write has reached the hardware before udelay().
> > +		 */
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(15);
> > +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				  IMX95_PCIE_COLD_RST);
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(10);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)  {
> >  	reset_control_assert(imx_pcie->pciephy_reset);
> > @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.init_phy = imx95_pcie_init_phy,
> >  	},
> >  	[IMX8MQ_EP] = {
> > @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> >  		.init_phy = imx95_pcie_init_phy,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.epc_features = &imx95_pcie_epc_features,
> >  		.mode = DW_PCIE_EP_TYPE,
> >  	},
> > --
> > 2.37.1
> >
> 
> --
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