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Message-ID: <CAMuHMdUpqw-bSmg1FZU72wvyH-bGCs4FwZKF6=aWkBVDnUEs_g@mail.gmail.com>
Date: Tue, 15 Apr 2025 16:35:01 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and
CLK_MON bits for clock state validation
On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Update the clock enable/disable logic to follow the latest hardware
> manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to
> confirm the clock state.
>
> According to the manual, enabling a clock requires setting the CPG_CLK_ON
> bit and verifying the clock has started using the CPG_CLK_MON bit.
> Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and
> confirming the clock has stopped via the CPG_CLK_MON bit.
>
> Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
> validate CLK_ON for a more accurate clock status evaluation.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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