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Message-ID: <86zfghjmmy.wl-maz@kernel.org>
Date: Tue, 15 Apr 2025 19:38:29 +0100
From: Marc Zyngier <maz@...nel.org>
To: D Scott Phillips <scott@...amperecomputing.com>
Cc: Catalin Marinas <catalin.marinas@....com>,
James Clark <james.clark@...aro.org>,
James Morse <james.morse@....com>,
Joey Gouly <joey.gouly@....com>,
Kevin Brodsky <kevin.brodsky@....com>,
Mark Brown <broonie@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Oliver Upton <oliver.upton@...ux.dev>,
"Rob Herring (Arm)" <robh@...nel.org>,
Shameer Kolothum <shameerali.kolothum.thodi@...wei.com>,
Shiqi Liu <shiqiliu@...t.edu.cn>,
Will Deacon <will@...nel.org>,
Yicong Yang <yangyicong@...ilicon.com>,
kvmarm@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org (open list)
Subject: Re: [PATCH 2/2] arm64: errata: Work around AmpereOne's erratum AC04_CPU_23
On Tue, 15 Apr 2025 16:47:11 +0100,
D Scott Phillips <scott@...amperecomputing.com> wrote:
>
> Updates to HCR_EL2 can rarely corrupt simultaneous translations from
> either earlier translations (back to the previous dsb) or later
> translations (up to the next isb). Put a dsb before and isb after writes
> to HCR_EL2.
If the write to HCR_EL2 can corrupt translations, what guarantees that
such write placed on a page boundary (therefore requiring another TLB
lookup to continue in sequence) will be able to get to the ISB?
M.
--
Without deviation from the norm, progress is not possible.
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