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Message-ID: <61fef9052b2034e5b4ffa1fa6ce481667d8ea6b1.1744692494.git.nicolinc@nvidia.com>
Date: Mon, 14 Apr 2025 21:57:41 -0700
From: Nicolin Chen <nicolinc@...dia.com>
To: <will@...nel.org>, <robin.murphy@....com>, <jgg@...dia.com>
CC: <joro@...tes.org>, <kevin.tian@...el.com>, <praan@...gle.com>,
<nathan@...nel.org>, <yi.l.liu@...el.com>, <peterz@...radead.org>,
<mshavit@...gle.com>, <jsnitsel@...hat.com>, <smostafa@...gle.com>,
<jeff.johnson@....qualcomm.com>, <zhangzekun11@...wei.com>,
<linux-arm-kernel@...ts.infradead.org>, <iommu@...ts.linux.dev>,
<linux-kernel@...r.kernel.org>, <shameerali.kolothum.thodi@...wei.com>
Subject: [PATCH v2 06/11] iommu/arm-smmu-v3: Introduce arm_smmu_s2_parent_tlb_ invalidation helpers
An S2 nest_parent domain can be shared across vSMMUs in the same VM, since
the S2 domain is basically the IPA mappings for the entire RAM of the VM.
Meanwhile, each vSMMU can have its own VMID, so the VMID allocation should
be done per vSMMU instance v.s. per S2 nest_parent domain.
However, an S2 domain can be also allocated when a physical SMMU instance
doesn't support S1. So, the structure has to retain the s2_cfg and vmid.
Add a per-domain "vsmmus" list pairing with a spinlock, maintaining a list
of vSMMUs in the S2 parent domain.
Provide two arm_smmu_s2_parent_tlb_ helpers that will be used for nesting
cases to invalidate S2 cache using vsmmu->vmid by iterating this "vsmmus"
list.
Signed-off-by: Nicolin Chen <nicolinc@...dia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 22 ++++++++
.../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 53 +++++++++++++++++++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +
3 files changed, 77 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 7b47f4408a7a..7d76d8ac9acc 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -859,6 +859,10 @@ struct arm_smmu_domain {
struct arm_smmu_ctx_desc cd;
struct arm_smmu_s2_cfg s2_cfg;
};
+ struct {
+ struct list_head list;
+ spinlock_t lock;
+ } vsmmus;
struct iommu_domain domain;
@@ -1081,6 +1085,7 @@ struct arm_vsmmu {
struct arm_smmu_device *smmu;
struct arm_smmu_domain *s2_parent;
u16 vmid;
+ struct list_head vsmmus_elm; /* arm_smmu_domain::vsmmus::list */
};
#if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD)
@@ -1094,6 +1099,11 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *state,
void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state);
void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master);
int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt);
+
+void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent);
+void arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent,
+ unsigned long iova, size_t size,
+ size_t granule, bool leaf);
#else
#define arm_smmu_hw_info NULL
#define arm_vsmmu_alloc NULL
@@ -1119,6 +1129,18 @@ static inline int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster,
{
return -EOPNOTSUPP;
}
+
+static inline void
+arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent)
+{
+}
+
+static inline void
+arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent,
+ unsigned long iova, size_t size,
+ size_t granule, bool leaf)
+{
+}
#endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */
#endif /* _ARM_SMMU_V3_H */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
index 6cd01536c966..45ba68a1b59a 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
@@ -30,6 +30,54 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type)
return info;
}
+void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent)
+{
+ struct arm_vsmmu *vsmmu, *next;
+ unsigned long flags;
+
+ spin_lock_irqsave(&s2_parent->vsmmus.lock, flags);
+ list_for_each_entry_safe(vsmmu, next, &s2_parent->vsmmus.list,
+ vsmmus_elm) {
+ arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid);
+ }
+ spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags);
+}
+
+void arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent,
+ unsigned long iova, size_t size,
+ size_t granule, bool leaf)
+{
+ struct arm_smmu_cmdq_ent cmd = { .tlbi = { .leaf = leaf } };
+ struct arm_vsmmu *vsmmu, *next;
+ unsigned long flags;
+
+ spin_lock_irqsave(&s2_parent->vsmmus.lock, flags);
+ list_for_each_entry_safe(vsmmu, next, &s2_parent->vsmmus.list,
+ vsmmus_elm) {
+ cmd.tlbi.vmid = vsmmu->vmid;
+
+ /* Must flush all the nested S1 ASIDs when S2 domain changes */
+ cmd.opcode = CMDQ_OP_TLBI_NH_ALL;
+ arm_smmu_cmdq_issue_cmd_with_sync(vsmmu->smmu, &cmd);
+ cmd.opcode = CMDQ_OP_TLBI_S2_IPA;
+ __arm_smmu_tlb_inv_range(vsmmu->smmu, &cmd, iova, size, granule,
+ &s2_parent->domain);
+ }
+ spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags);
+}
+
+static void arm_vsmmu_destroy(struct iommufd_viommu *viommu)
+{
+ struct arm_vsmmu *vsmmu = container_of(viommu, struct arm_vsmmu, core);
+ unsigned long flags;
+
+ spin_lock_irqsave(&vsmmu->s2_parent->vsmmus.lock, flags);
+ list_del(&vsmmu->vsmmus_elm);
+ spin_unlock_irqrestore(&vsmmu->s2_parent->vsmmus.lock, flags);
+ /* Must flush S2 vmid after delinking vSMMU */
+ arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid);
+}
+
static void arm_smmu_make_nested_cd_table_ste(
struct arm_smmu_ste *target, struct arm_smmu_master *master,
struct arm_smmu_nested_domain *nested_domain, bool ats_enabled)
@@ -380,6 +428,7 @@ static int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu,
}
static const struct iommufd_viommu_ops arm_vsmmu_ops = {
+ .destroy = arm_vsmmu_destroy,
.alloc_domain_nested = arm_vsmmu_alloc_domain_nested,
.cache_invalidate = arm_vsmmu_cache_invalidate,
};
@@ -394,6 +443,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev,
struct arm_smmu_master *master = dev_iommu_priv_get(dev);
struct arm_smmu_domain *s2_parent = to_smmu_domain(parent);
struct arm_vsmmu *vsmmu;
+ unsigned long flags;
if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3)
return ERR_PTR(-EOPNOTSUPP);
@@ -433,6 +483,9 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev,
vsmmu->s2_parent = s2_parent;
/* FIXME Move VMID allocation from the S2 domain allocation to here */
vsmmu->vmid = s2_parent->s2_cfg.vmid;
+ spin_lock_irqsave(&s2_parent->vsmmus.lock, flags);
+ list_add_tail(&vsmmu->vsmmus_elm, &s2_parent->vsmmus.list);
+ spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags);
return &vsmmu->core;
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 07d435562da2..df87880e2a29 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3256,6 +3256,8 @@ arm_smmu_domain_alloc_paging_flags(struct device *dev, u32 flags,
}
smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
smmu_domain->nest_parent = true;
+ INIT_LIST_HEAD(&smmu_domain->vsmmus.list);
+ spin_lock_init(&smmu_domain->vsmmus.lock);
break;
case IOMMU_HWPT_ALLOC_DIRTY_TRACKING:
case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_PASID:
--
2.43.0
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